Volume 2B Instruction Set Reference N-Z (794102), страница 61
Текст из файла (страница 61)
If the VMCS field is longer, then the high bitsof the field are cleared to 0.Note that any faults resulting from accessing a memory source operand occur afterdetermining, in the operation section below, that the VMCS pointer is valid but beforedetermining if the destination VMCS field is supported.OperationIF (not in VMX operation) or (RFLAGS.VM = 1) or(IA32_EFER.LMA = 1 and CS.L = 0)THEN #UD;ELSIF in VMX non-root operationTHEN VMexit;ELSIF CPL > 0THEN #GP(0);ELSIF current-VMCS pointer is not validTHEN VMfailInvalid;ELSIF register destination operand does not correspond to any VMCS fieldTHEN VMfailValid(VMREAD/VMWRITE from/to unsupported VMCS component);ELSIF VMCS field indexed by register destination operand is read-only)THEN VMfailValid(VMWRITE to read-only VMCS component);ELSEVMCS field indexed by register destination operand ← SRC;5-22 Vol.
2BVMWRITE—Write Field to Virtual-Machine Control StructureVMX INSTRUCTION REFERENCEVMsucceed;FI;Flags AffectedSee the operation section and Section 5.2.Use of PrefixesLOCKCauses #UDREP*Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ)Segment overrides Treated normallyOperand sizeCauses #UDAddress sizeTreated normallyREXRegister extensions treated normally; operand-size overridesignoredProtected Mode Exceptions#GP(0)If the current privilege level is not 0.If a memory source operand effective address is outside the CS,DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains an unusable segment.If the source operand is located in an execute-only codesegment.#PF(fault-code)If a page fault occurs in accessing a memory source operand.#SS(0)If a memory source operand effective address is outside the SSsegment limit.If the SS register contains an unusable segment.#UDIf not in VMX operation.Real-Address Mode Exceptions#UDA logical processor cannot be in real-address mode while in VMXoperation and the VMWRITE instruction is not recognizedoutside VMX operation.Virtual-8086 Mode Exceptions#UDThe VMWRITE instruction is not recognized in virtual-8086mode.Compatibility Mode Exceptions#UDThe VMWRITE instruction is not recognized in compatibilitymode.VMWRITE—Write Field to Virtual-Machine Control StructureVol.
2B 5-23VMX INSTRUCTION REFERENCE64-Bit Mode Exceptions#GP(0)If the current privilege level is not 0.If the memory source operand is in the CS, DS, ES, FS, or GSsegments and the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs in accessing a memory source operand.#SS(0)If the memory source operand is in the SS segment and thememory address is in a non-canonical form.#UDIf not in VMX operation.5-24 Vol. 2BVMWRITE—Write Field to Virtual-Machine Control StructureVMX INSTRUCTION REFERENCEVMXOFF—Leave VMX OperationOpcodeInstructionDescription0F 01 C4VMXOFFLeaves VMX operation.DescriptionTakes the logical processor out of VMX operation, unblocks INIT signals, re-enablesA20M, and clears any address-range monitoring.1OperationIF (not in VMX operation) or (RFLAGS.VM = 1) or(IA32_EFER.LMA = 1 and CS.L = 0)THEN #UD;ELSIF in VMX non-root operationTHEN VMexit;ELSIF CPL > 0THEN #GP(0);ELSIF dual-monitor treatment of SMIs and SMM is activeTHEN VMfail(VMXOFF under dual-monitor treatment of SMIs and SMM);ELSEleave VMX operation;unblock INIT;unblock and enable A20M;clear address-range monitoring;VMsucceed;FI;Flags AffectedSee the operation section and Section 5.2.Use of PrefixesLOCKCauses #UDREP*Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ)Segment overrides IgnoredOperand sizeCauses #UD1.
See the information on MONITOR/MWAIT in Chapter 7, “Multiple-Processor Management,” of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.VMXOFF—Leave VMX OperationVol. 2B 5-25VMX INSTRUCTION REFERENCEAddress sizeIgnoredREXIgnoredProtected Mode Exceptions#GP(0)If executed in VMX root operation with CPL > 0.#UDIf executed outside VMX operation.Real-Address Mode Exceptions#UDA logical processor cannot be in real-address mode while in VMXoperation and the VMXOFF instruction is not recognized outsideVMX operation.Virtual-8086 Mode Exceptions#UDThe VMXOFF instruction is not recognized in virtual-8086 mode.Compatibility Mode Exceptions#UDThe VMXOFF instruction is not recognized in compatibility mode.64-Bit Mode Exceptions#GP(0)If executed in VMX root operation with CPL > 0.#UDIf executed outside VMX operation.5-26 Vol.
2BVMXOFF—Leave VMX OperationVMX INSTRUCTION REFERENCEVMXON—Enter VMX OperationOpcodeInstructionDescriptionF3 0F C7 /6VMXON m64Enter VMX root operation.DescriptionPuts the logical processor in VMX operation with no current VMCS, blocks INITsignals, disables A20M, and clears any address-range monitoring established by theMONITOR instruction.1The operand of this instruction is a 4KB-aligned physical address (the VMXONpointer) that references the VMXON region, which the logical processor may use tosupport VMX operation. This operand is always 64 bits and is always in memory.OperationIF (register operand) or (CR4.VMXE = 0) or (CR0.PE = 0) or (RFLAGS.VM = 1) or(IA32_EFER.LMA = 1 and CS.L = 0)THEN #UD;ELSIF not in VMX operationTHENIF (CPL > 0) or (in A20M mode) or(the values of CR0 and CR4 are supported in VMX operation2) or(bit 0 (lock bit) of IA32_FEATURE_CONTROL MSR is clear) or(bit 2 of IA32_FEATURE_CONTROL MSR is clear)THEN #GP(0);ELSEaddr ← contents of 64-bit in-memory source operand;IF addr is not 4KB-aligned or(processor supports Intel 64 architecture andaddr sets any bits beyond the VMX physical-address width) or(processor does not support Intel 64 architecture andaddr sets any bits in the range 63:32)THEN VMfailInvalid;ELSErev ← 32 bits located at physical address addr;IF rev ≠ VMCS revision identifier supported by processorTHEN VMfailInvalid;1.
See the information on MONITOR/MWAIT in Chapter 7, “Multiple-Processor Management,” of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.2. See Section 19.8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume3B.VMXON—Enter VMX OperationVol. 2B 5-27VMX INSTRUCTION REFERENCEELSEcurrent-VMCS pointer ← FFFFFFFF_FFFFFFFFH;enter VMX operation;block INIT signals;block and disable A20M;clear address-range monitoring;VMsucceed;FI;FI;FI;ELSIF in VMX non-root operationTHEN VMexit;ELSIF CPL > 0THEN #GP(0);ELSE VMfail(“VMXON executed in VMX root operation”);FI;Flags AffectedSee the operation section and Section 5.2.Use of PrefixesLOCKCauses #UDREP*Ignored (includes REPNE/REPNZ and REP/REPE/REPZ)Segment overrides Treated normallyOperand sizeIgnoredAddress sizeTreated normallyREXRegister extensions treated normally; operand-size overridesignoredProtected Mode Exceptions#GP(0)If executed outside VMX operation with CPL>0 or with invalidCR0 or CR4 fixed bits.If executed in A20M mode.If the memory source operand effective address is outside theCS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains an unusable segment.If the source operand is located in an execute-only codesegment.#PF(fault-code)5-28 Vol.
2BIf a page fault occurs in accessing the memory source operand.VMXON—Enter VMX OperationVMX INSTRUCTION REFERENCE#SS(0)If the memory source operand effective address is outside theSS segment limit.If the SS register contains an unusable segment.#UDIf operand is a register.If executed with CR4.VMXE = 0.Real-Address Mode Exceptions#UDThe VMXON instruction is not recognized in real-address mode.Virtual-8086 Mode Exceptions#UDThe VMXON instruction is not recognized in virtual-8086 mode.Compatibility Mode Exceptions#UDThe VMXON instruction is not recognized in compatibility mode.64-Bit Mode Exceptions#GP(0)If executed outside VMX operation with CPL > 0 or with invalidCR0 or CR4 fixed bits.If executed in A20M mode.If the source operand is in the CS, DS, ES, FS, or GS segmentsand the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs in accessing the memory source operand.#SS(0)If the source operand is in the SS segment and the memoryaddress is in a non-canonical form.#UDIf operand is a register.If executed with CR4.VMXE = 0.VMXON—Enter VMX OperationVol.
2B 5-29VMX INSTRUCTION REFERENCE5-30 Vol. 2BVMXON—Enter VMX OperationAPPENDIX AOPCODE MAPUse the opcode tables in this chapter to interpret Intel 64 and IA-32 architectureobject code. Instructions are divided into encoding groups:•1-byte, 2-byte and 3-byte opcode encodings are used to encode integer, system,MMX technology, SSE/SSE2/SSE3/SSSE3, and VMX instructions. Maps for theseinstructions are given in Table A-2 through Table A-6.•Escape opcodes (in the format: ESC character, opcode, ModR/M byte) are usedfor floating-point instructions. The maps for these instructions are provided inTable A-7 through Table A-22.NOTEAll blanks in opcode maps are reserved and must not be used. Do notdepend on the operation of undefined or blank opcodes.A.1USING OPCODE TABLESTables in this appendix list opcodes of instructions (including required instructionprefixes, opcode extensions in associated ModR/M byte).
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
