Volume 2B Instruction Set Reference N-Z (794102), страница 56
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See the summary chart atthe beginning of this section for encoding data and limits.This instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.IA-32 Architecture CompatibilityIA-32 processors earlier than the Intel486 processor do not recognize this instruction.
If this instruction is used, you should provide an equivalent code sequence thatruns on earlier processors.OperationTEMP ← SRC + DEST;SRC ← DEST;DEST ← TEMP;4-410 Vol. 2BXADD—Exchange and AddINSTRUCTION SET REFERENCE, N-ZFlags AffectedThe CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition,which is stored in the destination operand.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.XADD—Exchange and AddVol.
2B 4-411INSTRUCTION SET REFERENCE, N-Z64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.4-412 Vol.
2BXADD—Exchange and AddINSTRUCTION SET REFERENCE, N-ZXCHG—Exchange Register/Memory with RegisterOpcodeInstruction64-BitModeCompat/Leg ModeDescription90+rwXCHG AX, r16ValidValidExchange r16 with AX.90+rwXCHG r16, AXValidValidExchange AX with r16.90+rdXCHG EAX, r32ValidValidExchange r32 with EAX.REX.W + 90+rdXCHG RAX, r64ValidN.E.Exchange r64 with RAX.90+rdXCHG r32, EAXValidValidExchange EAX with r32.REX.W + 90+rdXCHG r64, RAXValidN.E.Exchange RAX with r64.86 /rXCHG r/m8, r8ValidValidExchange r8 (byte register) withbyte from r/m8.REX + 86 /rXCHG r/m8*, r8*ValidN.E.Exchange r8 (byte register) withbyte from r/m8.86 /rXCHG r8, r/m8ValidValidExchange byte from r/m8 withr8 (byte register).REX + 86 /rXCHG r8*, r/m8*ValidN.E.Exchange byte from r/m8 withr8 (byte register).87 /rXCHG r/m16, r16ValidValidExchange r16 with word fromr/m16.87 /rXCHG r16, r/m16ValidValidExchange word from r/m16 withr16.87 /rXCHG r/m32, r32ValidValidExchange r32 with doublewordfrom r/m32.REX.W + 87 /rXCHG r/m64, r64ValidN.E.Exchange r64 with quadwordfrom r/m64.87 /rXCHG r32, r/m32ValidValidExchange doubleword fromr/m32 with r32.REX.W + 87 /rXCHG r64, r/m64ValidN.E.Exchange quadword from r/m64with r64.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.DescriptionExchanges the contents of the destination (first) and source (second) operands.
Theoperands can be two general-purpose registers or a register and a memory location.If a memory operand is referenced, the processor’s locking protocol is automaticallyimplemented for the duration of the exchange operation, regardless of the presenceXCHG—Exchange Register/Memory with RegisterVol. 2B 4-413INSTRUCTION SET REFERENCE, N-Zor absence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefixdescription in this chapter for more information on the locking protocol.)This instruction is useful for implementing semaphores or similar data structures forprocess synchronization. (See “Bus Locking” in Chapter 7 of the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 3A, for more information on buslocking.)The XCHG instruction can also be used instead of the BSWAP instruction for 16-bitoperands.In 64-bit mode, the instruction’s default operation size is 32 bits.
Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationTEMP ← DEST;DEST ← SRC;SRC ← TEMP;Flags AffectedNone.Protected Mode Exceptions#GP(0)If either operand is in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.4-414 Vol.
2BXCHG—Exchange Register/Memory with RegisterINSTRUCTION SET REFERENCE, N-Z#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.XCHG—Exchange Register/Memory with RegisterVol.
2B 4-415INSTRUCTION SET REFERENCE, N-ZXLAT/XLATB—Table Look-up TranslationOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD7XLAT m8ValidValidSet AL to memory byte DS:[(E)BX +unsigned AL].D7XLATBValidValidSet AL to memory byte DS:[(E)BX +unsigned AL].REX.W + D7XLATBValidN.E.Set AL to memory byte [RBX +unsigned AL].DescriptionLocates a byte entry in a table in memory, using the contents of the AL register as atable index, then copies the contents of the table entry back into the AL register.
Theindex in the AL register is treated as an unsigned integer. The XLAT and XLATBinstructions get the base address of the table in memory from either the DS:EBX orthe DS:BX registers (depending on the address-size attribute of the instruction, 32 or16, respectively). (The DS segment may be overridden with a segment overrideprefix.)At the assembly-code level, two forms of this instruction are allowed: the “explicitoperand” form and the “no-operand” form. The explicit-operand form (specified withthe XLAT mnemonic) allows the base address of the table to be specified explicitlywith a symbol.
This explicit-operands form is provided to allow documentation;however, note that the documentation provided by this form can be misleading. Thatis, the symbol does not have to specify the correct base address. The base address isalways specified by the DS:(E)BX registers, which must be loaded correctly beforethe XLAT instruction is executed.The no-operands form (XLATB) provides a “short form” of the XLAT instructions.
Herealso the processor assumes that the DS:(E)BX registers contain the base address ofthe table.In 64-bit mode, operation is similar to that in legacy or compatibility mode. AL isused to specify the table index (the operand size is fixed at 8 bits). RBX, however, isused to specify the table’s base address.
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