Volume 2B Instruction Set Reference N-Z (794102), страница 40
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A special opcode encoding is provided for a countof 1.The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform thesame operation; they shift the bits in the destination operand to the left (towardmore significant bit locations). For each shift count, the most significant bit of thedestination operand is shifted into the CF flag, and the least significant bit is cleared(see Figure 7-7 in the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 1).The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bitsof the destination operand to the right (toward less significant bit locations).
For eachshift count, the least significant bit of the destination operand is shifted into the CFflag, and the most significant bit is either set or cleared depending on the instructiontype. The SHR instruction clears the most significant bit (see Figure 7-8 in the Intel®64 and IA-32 Architectures Software Developer’s Manual, Volume 1); the SARinstruction sets or clears the most significant bit to correspond to the sign (mostsignificant bit) of the original value in the destination operand.
In effect, the SARinstruction fills the empty bit position’s shifted value with the sign of the unshiftedvalue (see Figure 7-9 in the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 1).The SAR and SHR instructions can be used to perform signed or unsigned division,respectively, of the destination operand by powers of 2. For example, using the SARinstruction to shift a signed integer 1 bit to the right divides the value by 2.Using the SAR instruction to perform a division operation does not produce the sameresult as the IDIV instruction. The quotient from the IDIV instruction is roundedtoward zero, whereas the “quotient” of the SAR instruction is rounded toward negative infinity.
This difference is apparent only for negative numbers. For example,when the IDIV instruction is used to divide -9 by 4, the result is -2 with a remainderof -1. If the SAR instruction is used to shift -9 right by two bits, the result is -3 andthe “remainder” is +3; however, the SAR instruction stores only the most significantbit of the remainder (in the CF flag).The OF flag is affected only on 1-bit shifts. For left shifts, the OF flag is set to 0 if themost-significant bit of the result is the same as the CF flag (that is, the top two bitsof the original operand were the same); otherwise, it is set to 1. For the SAR instruction, the OF flag is cleared for all 1-bit shifts. For the SHR instruction, the OF flag isset to the most-significant bit of the original operand.SAL/SAR/SHL/SHR—ShiftVol.
2B 4-283INSTRUCTION SET REFERENCE, N-ZIn 64-bit mode, the instruction’s default operation size is 32 bits and the mask widthfor CL is 5 bits. Using a REX prefix in the form of REX.R permits access to additionalregisters (R8-R15). Using a REX prefix in the form of REX.W promotes operation to64-bits and sets the mask width for CL to 6 bits. See the summary chart at the beginning of this section for encoding data and limits.IA-32 Architecture CompatibilityThe 8086 does not mask the shift count.
However, all other IA-32 processors(starting with the Intel 286 processor) do mask the shift count to 5 bits, resulting ina maximum count of 31. This masking is done in all operating modes (including thevirtual-8086 mode) to reduce the maximum execution time of the instructions.OperationIF 64-Bit Mode and using REX.WTHENcountMASK ← 3FH;ELSEcountMASK ← 1FH;FItempCOUNT ← (COUNT AND countMASK);tempDEST ← DEST;WHILE (tempCOUNT ≠ 0)DOIF instruction is SAL or SHLTHENCF ← MSB(DEST);ELSE (* Instruction is SAR or SHR *)CF ← LSB(DEST);FI;IF instruction is SAL or SHLTHENDEST ← DEST ∗ 2;ELSEIF instruction is SARTHENDEST ← DEST / 2; (* Signed divide, rounding toward negative infinity *)ELSE (* Instruction is SHR *)DEST ← DEST / 2 ; (* Unsigned divide *)FI;FI;tempCOUNT ← tempCOUNT – 1;OD;4-284 Vol. 2BSAL/SAR/SHL/SHR—ShiftINSTRUCTION SET REFERENCE, N-Z(* Determine overflow for the various instructions *)IF (COUNT and countMASK) = 1THENIF instruction is SAL or SHLTHENOF ← MSB(DEST) XOR CF;ELSEIF instruction is SARTHENOF ← 0;ELSE (* Instruction is SHR *)OF ← MSB(tempDEST);FI;FI;ELSE IF (COUNT AND countMASK) = 0THENAll flags unchanged;ELSE (* COUNT not 1 or 0 *)OF ← undefined;FI;FI;Flags AffectedThe CF flag contains the value of the last bit shifted out of the destination operand; itis undefined for SHL and SHR instructions where the count is greater than or equal tothe size (in bits) of the destination operand.
The OF flag is affected only for 1-bitshifts (see “Description” above); otherwise, it is undefined. The SF, ZF, and PF flagsare set according to the result. If the count is 0, the flags are not affected. For a nonzero count, the AF flag is undefined.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.SAL/SAR/SHL/SHR—ShiftVol.
2B 4-285INSTRUCTION SET REFERENCE, N-Z#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.4-286 Vol.
2BSAL/SAR/SHL/SHR—ShiftINSTRUCTION SET REFERENCE, N-ZSBB—Integer Subtraction with BorrowOpcodeInstruction64-BitModeCompat/Leg ModeDescription1C ibSBB AL, imm8ValidValidSubtract with borrow imm8from AL.1D iwSBB AX, imm16ValidValidSubtract with borrow imm16from AX.1D idSBB EAX, imm32ValidValidSubtract with borrow imm32from EAX.REX.W + 1D idSBB RAX, imm32ValidN.E.Subtract with borrow signextended imm.32 to 64-bitsfrom RAX.80 /3 ibSBB r/m8, imm8ValidValidSubtract with borrow imm8from r/m8.REX + 80 /3 ibSBB r/m8*, imm8ValidN.E.Subtract with borrow imm8from r/m8.81 /3 iwSBB r/m16, imm16 ValidValidSubtract with borrow imm16from r/m16.81 /3 idSBB r/m32, imm32 ValidValidSubtract with borrow imm32from r/m32.REX.W + 81 /3 idSBB r/m64, imm32 ValidN.E.Subtract with borrow signextended imm32 to 64-bitsfrom r/m64.83 /3 ibSBB r/m16, imm8ValidValidSubtract with borrow signextended imm8 from r/m16.83 /3 ibSBB r/m32, imm8ValidValidSubtract with borrow signextended imm8 from r/m32.REX.W + 83 /3 ibSBB r/m64, imm8ValidN.E.Subtract with borrow signextended imm8 from r/m64.18 /rSBB r/m8, r8ValidValidSubtract with borrow r8from r/m8.REX + 18 /rSBB r/m8*, r8ValidN.E.Subtract with borrow r8from r/m8.19 /rSBB r/m16, r16ValidValidSubtract with borrow r16from r/m16.19 /rSBB r/m32, r32ValidValidSubtract with borrow r32from r/m32.REX.W + 19 /rSBB r/m64, r64ValidN.E.Subtract with borrow r64from r/m64.SBB—Integer Subtraction with BorrowVol.
2B 4-287INSTRUCTION SET REFERENCE, N-ZOpcodeInstruction64-BitModeCompat/Leg ModeDescription1A /rSBB r8, r/m8ValidValidSubtract with borrow r/m8from r8.REX + 1A /rSBB r8*, r/m8*ValidN.E.Subtract with borrow r/m8from r8.1B /rSBB r16, r/m16ValidValidSubtract with borrow r/m16from r16.1B /rSBB r32, r/m32ValidValidSubtract with borrow r/m32from r32.REX.W + 1B /rSBB r64, r/m64ValidN.E.Subtract with borrow r/m64from r64.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.DescriptionAdds the source operand (second operand) and the carry (CF) flag, and subtracts theresult from the destination operand (first operand). The result of the subtraction isstored in the destination operand.
The destination operand can be a register or amemory location; the source operand can be an immediate, a register, or a memorylocation. (However, two memory operands cannot be used in one instruction.) Thestate of the CF flag represents a borrow from a previous subtraction.When an immediate value is used as an operand, it is sign-extended to the length ofthe destination operand format.The SBB instruction does not distinguish between signed or unsigned operands.Instead, the processor evaluates the result for both data types and sets the OF andCF flags to indicate a borrow in the signed or unsigned result, respectively.
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