Volume 2B Instruction Set Reference N-Z (794102), страница 67
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See Table B-11.•When used for integer instructions, the d bit is located at bit 1 of a 1-byte primaryopcode. Note that this bit does not appear as the symbol “d” in Table B-13; theactual encoding of the bit as 1 or 0 is given.•When used for floating-point instructions (in Table B-16), the d bit is shown as bit2 of the first byte of the primary opcode.Table B-11.
Encoding of Operation Direction (d) BitdSourceDestination0reg FieldModR/M or SIB Byte1ModR/M or SIB Bytereg FieldB-8 Vol. 2BINSTRUCTION FORMATS AND ENCODINGSB.1.5Other NotesTable B-12 contains notes on particular encodings. These notes are indicated in thetables shown in the following sections by superscripts.Table B-12. Notes on Instruction EncodingSymbolANoteA value of 11B in bits 7 and 6 of the ModR/M byte is reserved.B.2GENERAL-PURPOSE INSTRUCTION FORMATS ANDENCODINGS FOR NON-64-BIT MODESTable B-13 shows machine instruction formats and encodings for general purposeinstructions in non-64-bit modes.Table B-13.
General Purpose Instruction Formats and Encodingsfor Non-64-Bit ModesInstruction and FormatEncodingAAA – ASCII Adjust after Addition0011 0111AAD – ASCII Adjust AX before Division1101 0101 : 0000 1010AAM – ASCII Adjust AX after Multiply1101 0100 : 0000 1010AAS – ASCII Adjust AL after Subtraction0011 1111ADC – ADD with Carryregister1 to register20001 000w : 11 reg1 reg2register2 to register10001 001w : 11 reg1 reg2memory to register0001 001w : mod reg r/mregister to memory0001 000w : mod reg r/mimmediate to register1000 00sw : 11 010 reg : immediate dataimmediate to AL, AX, or EAX0001 010w : immediate dataimmediate to memory1000 00sw : mod 010 r/m : immediate dataADD – Addregister1 to register20000 000w : 11 reg1 reg2register2 to register10000 001w : 11 reg1 reg2memory to register0000 001w : mod reg r/mregister to memory0000 000w : mod reg r/mimmediate to register1000 00sw : 11 000 reg : immediate dataVol.
2B B-9INSTRUCTION FORMATS AND ENCODINGSTable B-13. General Purpose Instruction Formats and Encodingsfor Non-64-Bit Modes (Contd.)Instruction and FormatEncodingimmediate to AL, AX, or EAX0000 010w : immediate dataimmediate to memory1000 00sw : mod 000 r/m : immediate dataAND – Logical ANDregister1 to register20010 000w : 11 reg1 reg2register2 to register10010 001w : 11 reg1 reg2memory to register0010 001w : mod reg r/mregister to memory0010 000w : mod reg r/mimmediate to register1000 00sw : 11 100 reg : immediate dataimmediate to AL, AX, or EAX0010 010w : immediate dataimmediate to memory1000 00sw : mod 100 r/m : immediate dataARPL – Adjust RPL Field of Selectorfrom register0110 0011 : 11 reg1 reg2from memory0110 0011 : mod reg r/mBOUND – Check Array Against Bounds0110 0010 : modA reg r/mBSF – Bit Scan Forwardregister1, register20000 1111 : 1011 1100 : 11 reg1 reg2memory, register0000 1111 : 1011 1100 : mod reg r/mBSR – Bit Scan Reverseregister1, register20000 1111 : 1011 1101 : 11 reg1 reg2memory, register0000 1111 : 1011 1101 : mod reg r/mBSWAP – Byte Swap0000 1111 : 1100 1 regBT – Bit Testregister, immediate0000 1111 : 1011 1010 : 11 100 reg: imm8datamemory, immediate0000 1111 : 1011 1010 : mod 100 r/m : imm8dataregister1, register20000 1111 : 1010 0011 : 11 reg2 reg1memory, reg0000 1111 : 1010 0011 : mod reg r/mBTC – Bit Test and Complementregister, immediateB-10 Vol.
2B0000 1111 : 1011 1010 : 11 111 reg: imm8dataINSTRUCTION FORMATS AND ENCODINGSTable B-13. General Purpose Instruction Formats and Encodingsfor Non-64-Bit Modes (Contd.)Instruction and FormatEncodingmemory, immediate0000 1111 : 1011 1010 : mod 111 r/m : imm8dataregister1, register20000 1111 : 1011 1011 : 11 reg2 reg1memory, reg0000 1111 : 1011 1011 : mod reg r/mBTR – Bit Test and Resetregister, immediate0000 1111 : 1011 1010 : 11 110 reg: imm8datamemory, immediate0000 1111 : 1011 1010 : mod 110 r/m : imm8dataregister1, register20000 1111 : 1011 0011 : 11 reg2 reg1memory, reg0000 1111 : 1011 0011 : mod reg r/mBTS – Bit Test and Setregister, immediate0000 1111 : 1011 1010 : 11 101 reg: imm8datamemory, immediate0000 1111 : 1011 1010 : mod 101 r/m : imm8dataregister1, register20000 1111 : 1010 1011 : 11 reg2 reg1memory, reg0000 1111 : 1010 1011 : mod reg r/mCALL – Call Procedure (in same segment)direct1110 1000 : full displacementregister indirect1111 1111 : 11 010 regmemory indirect1111 1111 : mod 010 r/mCALL – Call Procedure (in other segment)direct1001 1010 : unsigned full offset, selectorindirect1111 1111 : mod 011 r/mCBW – Convert Byte to Word1001 1000CDQ – Convert Doubleword to Qword1001 1001CLC – Clear Carry Flag1111 1000CLD – Clear Direction Flag1111 1100CLI – Clear Interrupt Flag1111 1010Vol.
2B B-11INSTRUCTION FORMATS AND ENCODINGSTable B-13. General Purpose Instruction Formats and Encodingsfor Non-64-Bit Modes (Contd.)Instruction and FormatEncodingCLTS – Clear Task-Switched Flag in CR00000 1111 : 0000 0110CMC – Complement Carry Flag1111 0101CMP – Compare Two Operandsregister1 with register20011 100w : 11 reg1 reg2register2 with register10011 101w : 11 reg1 reg2memory with register0011 100w : mod reg r/mregister with memory0011 101w : mod reg r/mimmediate with register1000 00sw : 11 111 reg : immediate dataimmediate with AL, AX, or EAX0011 110w : immediate dataimmediate with memory1000 00sw : mod 111 r/m : immediate dataCMPS/CMPSB/CMPSW/CMPSD – CompareString Operands1010 011wCMPXCHG – Compare and Exchangeregister1, register20000 1111 : 1011 000w : 11 reg2 reg1memory, register0000 1111 : 1011 000w : mod reg r/mCPUID – CPU Identification0000 1111 : 1010 0010CWD – Convert Word to Doubleword1001 1001CWDE – Convert Word to Doubleword1001 1000DAA – Decimal Adjust AL after Addition0010 0111DAS – Decimal Adjust AL after Subtraction0010 1111DEC – Decrement by 1register1111 111w : 11 001 regregister (alternate encoding)0100 1 regmemory1111 111w : mod 001 r/mDIV – Unsigned DivideAL, AX, or EAX by register1111 011w : 11 110 regAL, AX, or EAX by memory1111 011w : mod 110 r/mENTER – Make Stack Frame for High LevelProcedure1100 1000 : 16-bit displacement : 8-bit level(L)HLT – Halt1111 0100B-12 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-13. General Purpose Instruction Formats and Encodingsfor Non-64-Bit Modes (Contd.)Instruction and FormatEncodingIDIV – Signed DivideAL, AX, or EAX by register1111 011w : 11 111 regAL, AX, or EAX by memory1111 011w : mod 111 r/mIMUL – Signed MultiplyAL, AX, or EAX with register1111 011w : 11 101 regAL, AX, or EAX with memory1111 011w : mod 101 regregister1 with register20000 1111 : 1010 1111 : 11 : reg1 reg2register with memory0000 1111 : 1010 1111 : mod reg r/mregister1 with immediate to register20110 10s1 : 11 reg1 reg2 : immediate datamemory with immediate to register0110 10s1 : mod reg r/m : immediate dataIN – Input From Portfixed port1110 010w : port numbervariable port1110 110wINC – Increment by 1reg1111 111w : 11 000 regreg (alternate encoding)0100 0 regmemory1111 111w : mod 000 r/mINS – Input from DX Port0110 110wINT n – Interrupt Type n1100 1101 : typeINT – Single-Step Interrupt 31100 1100INTO – Interrupt 4 on Overflow1100 1110INVD – Invalidate Cache0000 1111 : 0000 1000INVLPG – Invalidate TLB Entry0000 1111 : 0000 0001 : mod 111 r/mIRET/IRETD – Interrupt Return1100 1111Jcc – Jump if Condition is Met8-bit displacement0111 tttn : 8-bit displacementfull displacement0000 1111 : 1000 tttn : full displacementJCXZ/JECXZ – Jump on CX/ECX ZeroAddress-size prefix differentiates JCXZand JECXZ1110 0011 : 8-bit displacementVol.
2B B-13INSTRUCTION FORMATS AND ENCODINGSTable B-13. General Purpose Instruction Formats and Encodingsfor Non-64-Bit Modes (Contd.)Instruction and FormatEncodingJMP – Unconditional Jump (to same segment)short1110 1011 : 8-bit displacementdirect1110 1001 : full displacementregister indirect1111 1111 : 11 100 regmemory indirect1111 1111 : mod 100 r/mJMP – Unconditional Jump (to other segment)direct intersegment1110 1010 : unsigned full offset, selectorindirect intersegment1111 1111 : mod 101 r/mLAHF – Load Flags into AHRegister1001 1111LAR – Load Access Rights Bytefrom register0000 1111 : 0000 0010 : 11 reg1 reg2from memory0000 1111 : 0000 0010 : mod reg r/mLDS – Load Pointer to DS1100 0101 : modA reg r/mLEA – Load Effective Address1000 1101 : modA reg r/mLEAVE – High Level Procedure Exit1100 1001LES – Load Pointer to ES1100 0100 : modA reg r/mLFS – Load Pointer to FS0000 1111 : 1011 0100 : modA reg r/mLGDT – Load Global Descriptor Table Register0000 1111 : 0000 0001 : modA 010 r/mLGS – Load Pointer to GS0000 1111 : 1011 0101 : modA reg r/mLIDT – Load Interrupt Descriptor TableRegister0000 1111 : 0000 0001 : modA 011 r/mLLDT – Load Local Descriptor Table RegisterLDTR from register0000 1111 : 0000 0000 : 11 010 regLDTR from memory0000 1111 : 0000 0000 : mod 010 r/mLMSW – Load Machine Status Wordfrom register0000 1111 : 0000 0001 : 11 110 regfrom memory0000 1111 : 0000 0001 : mod 110 r/mLOCK – Assert LOCK# Signal Prefix1111 0000LODS/LODSB/LODSW/LODSD – Load StringOperand1010 110wB-14 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-13. General Purpose Instruction Formats and Encodingsfor Non-64-Bit Modes (Contd.)Instruction and FormatEncodingLOOP – Loop Count1110 0010 : 8-bit displacementLOOPZ/LOOPE – Loop Count while Zero/Equal1110 0001 : 8-bit displacementLOOPNZ/LOOPNE – Loop Count while notZero/Equal1110 0000 : 8-bit displacementLSL – Load Segment Limitfrom register0000 1111 : 0000 0011 : 11 reg1 reg2from memory0000 1111 : 0000 0011 : mod reg r/mLSS – Load Pointer to SS0000 1111 : 1011 0010 : modA reg r/mLTR – Load Task Registerfrom register0000 1111 : 0000 0000 : 11 011 regfrom memory0000 1111 : 0000 0000 : mod 011 r/mMOV – Move Dataregister1 to register21000 100w : 11 reg1 reg2register2 to register11000 101w : 11 reg1 reg2memory to reg1000 101w : mod reg r/mreg to memory1000 100w : mod reg r/mimmediate to register1100 011w : 11 000 reg : immediate dataimmediate to register (alternate encoding)1011 w reg : immediate dataimmediate to memory1100 011w : mod 000 r/m : immediate datamemory to AL, AX, or EAX1010 000w : full displacementAL, AX, or EAX to memory1010 001w : full displacementMOV – Move to/from Control RegistersCR0 from register0000 1111 : 0010 0010 : 11 000 regCR2 from register0000 1111 : 0010 0010 : 11 010regCR3 from register0000 1111 : 0010 0010 : 11 011 regCR4 from register0000 1111 : 0010 0010 : 11 100 regregister from CR0-CR40000 1111 : 0010 0000 : 11 eee regMOV – Move to/from Debug RegistersDR0-DR3 from register0000 1111 : 0010 0011 : 11 eee regDR4-DR5 from register0000 1111 : 0010 0011 : 11 eee regVol.
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