Volume 2B Instruction Set Reference N-Z (794102), страница 72
Текст из файла (страница 72)
2BINSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingSHR – Shift Rightregister by 10100 000B 1101 000w : 11 101 regbyteregister by 10100 000B 1101 0000 : 11 101 byteregqwordregister by 10100 100B 1101 0001 : 11 101 qwordregmemory by 10100 00XB 1101 000w : mod 101 r/mmemory8 by 10100 00XB 1101 0000 : mod 101 r/mmemory64 by 10100 10XB 1101 0001 : mod 101 r/mregister by CL0100 000B 1101 001w : 11 101 regbyteregister by CL0100 000B 1101 0010 : 11 101 byteregqwordregister by CL0100 100B 1101 0011 : 11 101 qwordregmemory by CL0100 00XB 1101 001w : mod 101 r/mmemory8 by CL0100 00XB 1101 0010 : mod 101 r/mmemory64 by CL0100 10XB 1101 0011 : mod 101 r/mregister by immediate count0100 000B 1100 000w : 11 101 reg : imm8byteregister by immediate count0100 000B 1100 0000 : 11 101 reg : imm8qwordregister by immediate count0100 100B 1100 0001 : 11 101 reg : imm8memory by immediate count0100 00XB 1100 000w : mod 101 r/m : imm8memory8 by immediate count0100 00XB 1100 0000 : mod 101 r/m : imm8memory64 by immediate count0100 10XB 1100 0001 : mod 101 r/m : imm8SHRD – Double Precision Shift Rightregister by immediate count0100 0R0B 0000 1111 : 1010 1100 : 11 reg2reg1 : imm8qwordregister by immediate80100 1R0B 0000 1111 : 1010 1100 : 11qwordreg2 qwordreg1 : imm8memory by immediate count0100 00XB 0000 1111 : 1010 1100 : mod regr/m : imm8memory64 by immediate80100 1RXB 0000 1111 : 1010 1100 : modqwordreg r/m : imm8register by CL0100 000B 0000 1111 : 1010 1101 : 11 reg2reg1Vol.
2B B-47INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingqwordregister by CL0100 1R0B 0000 1111 : 1010 1101 : 11qwordreg2 qwordreg1memory by CL0000 1111 : 1010 1101 : mod reg r/mmemory64 by CL0100 1RXB 0000 1111 : 1010 1101 : modqwordreg r/mSIDT – Store Interrupt Descriptor TableRegister0000 1111 : 0000 0001 : modA 001 r/mSLDT – Store Local Descriptor Table Registerto register0100 000B 0000 1111 : 0000 0000 : 11 000regto memory0100 00XB 0000 1111 : 0000 0000 : mod000 r/mSMSW – Store Machine Status Wordto register0100 000B 0000 1111 : 0000 0001 : 11 100regto memory0100 00XB 0000 1111 : 0000 0001 : mod100 r/mSTC – Set Carry Flag1111 1001STD – Set Direction Flag1111 1101STI – Set Interrupt Flag1111 1011STOS/STOSB/STOSW/STOSD/STOSQ – StoreString Datastore string data1010 101wstore string data (RAX at address RDI)0100 1000 1010 1011STR – Store Task Registerto register0100 000B 0000 1111 : 0000 0000 : 11 001regto memory0100 00XB 0000 1111 : 0000 0000 : mod001 r/mSUB – Integer Subtractionregister1 from register2B-48 Vol.
2B0100 0R0B 0010 100w : 11 reg1 reg2INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingbyteregister1 from byteregister20100 0R0B 0010 1000 : 11 bytereg1bytereg2qwordregister1 from qwordregister20100 1R0B 0010 1000 : 11 qwordreg1qwordreg2register2 from register10100 0R0B 0010 101w : 11 reg1 reg2byteregister2 from byteregister10100 0R0B 0010 1010 : 11 bytereg1bytereg2qwordregister2 from qwordregister10100 1R0B 0010 1011 : 11 qwordreg1qwordreg2memory from register0100 00XB 0010 101w : mod reg r/mmemory8 from byteregister0100 0RXB 0010 1010 : mod bytereg r/mmemory64 from qwordregister0100 1RXB 0010 1011 : mod qwordreg r/mregister from memory0100 0RXB 0010 100w : mod reg r/mbyteregister from memory80100 0RXB 0010 1000 : mod bytereg r/mqwordregister from memory80100 1RXB 0010 1000 : mod qwordreg r/mimmediate from register0100 000B 1000 00sw : 11 101 reg : immimmediate8 from byteregister0100 000B 1000 0000 : 11 101 bytereg :imm8immediate32 from qwordregister0100 100B 1000 0001 : 11 101 qwordreg :imm32immediate8 from qwordregister0100 100B 1000 0011 : 11 101 qwordreg :imm8immediate from AL, AX, or EAX0100 000B 0010 110w : immimmediate32 from RAX0100 1000 0010 1101 : imm32immediate from memory0100 00XB 1000 00sw : mod 101 r/m : immimmediate8 from memory80100 00XB 1000 0000 : mod 101 r/m : imm8immediate32 from memory640100 10XB 1000 0001 : mod 101 r/m : imm32immediate8 from memory640100 10XB 1000 0011 : mod 101 r/m : imm8SWAPGS – Swap GS Base RegisterGS base register value for value in MSRC0000102H0000 1111 0000 0001 [this oneincomplete]Vol.
2B B-49INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingSYSCALL – Fast System Callfast call to privilege level 0 systemprocedures0000 1111 0000 0101SYSRET – Return From Fast System Callreturn from fast system call0000 1111 0000 0111TEST – Logical Compareregister1 and register20100 0R0B 1000 010w : 11 reg1 reg2byteregister1 and byteregister20100 0R0B 1000 0100 : 11 bytereg1bytereg2qwordregister1 and qwordregister20100 1R0B 1000 0101 : 11 qwordreg1qwordreg2memory and register0100 0R0B 1000 010w : mod reg r/mmemory8 and byteregister0100 0RXB 1000 0100 : mod bytereg r/mmemory64 and qwordregister0100 1RXB 1000 0101 : mod qwordreg r/mimmediate and register0100 000B 1111 011w : 11 000 reg : immimmediate8 and byteregister0100 000B 1111 0110 : 11 000 bytereg :imm8immediate32 and qwordregister0100 100B 1111 0111 : 11 000 bytereg :imm8immediate and AL, AX, or EAX0100 000B 1010 100w : immimmediate32 and RAX0100 1000 1010 1001 : imm32immediate and memory0100 00XB 1111 011w : mod 000 r/m : immimmediate8 and memory80100 1000 1111 0110 : mod 000 r/m : imm8immediate32 and memory640100 1000 1111 0111 : mod 000 r/m : imm32UD2 – Undefined instruction0000 FFFF : 0000 1011VERR – Verify a Segment for Readingregister0100 000B 0000 1111 : 0000 0000 : 11 100regmemory0100 00XB 0000 1111 : 0000 0000 : mod100 r/mB-50 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingVERW – Verify a Segment for Writingregister0100 000B 0000 1111 : 0000 0000 : 11 101regmemory0100 00XB 0000 1111 : 0000 0000 : mod101 r/mWAIT – Wait1001 1011WBINVD – Writeback and Invalidate DataCache0000 1111 : 0000 1001WRMSR – Write to Model-Specific Registerwrite EDX:EAX to ECX specified MSRwrite RDX[31:0]:RAX[31:0] to RCX specifiedMSR0000 1111 : 0011 00000100 1000 0000 1111 : 0011 0000XADD – Exchange and Addregister1, register20100 0R0B 0000 1111 : 1100 000w : 11 reg2reg1byteregister1, byteregister20100 0R0B 0000 1111 : 1100 0000 : 11bytereg2 bytereg1qwordregister1, qwordregister20100 0R0B 0000 1111 : 1100 0001 : 11qwordreg2 qwordreg1memory, register0100 0RXB 0000 1111 : 1100 000w : modreg r/mmemory8, bytereg0100 1RXB 0000 1111 : 1100 0000 : modbytereg r/mmemory64, qwordreg0100 1RXB 0000 1111 : 1100 0001 : modqwordreg r/mXCHG – Exchange Register/Memory withRegisterregister1 with register21000 011w : 11 reg1 reg2AX or EAX with register1001 0 regmemory with register1000 011w : mod reg r/mXLAT/XLATB – Table Look-up TranslationAL to byte DS:[(E)BX + unsigned AL]1101 0111AL to byte DS:[RBX + unsigned AL]0100 1000 1101 0111Vol.
2B B-51INSTRUCTION FORMATS AND ENCODINGSTable B-15. General Purpose Instruction Formats and Encodingsfor 64-Bit Mode (Contd.)Instruction and FormatEncodingXOR – Logical Exclusive ORregister1 to register20100 0RXB 0011 000w : 11 reg1 reg2byteregister1 to byteregister20100 0R0B 0011 0000 : 11 bytereg1bytereg2qwordregister1 to qwordregister20100 1R0B 0011 0001 : 11 qwordreg1qwordreg2register2 to register10100 0R0B 0011 001w : 11 reg1 reg2byteregister2 to byteregister10100 0R0B 0011 0010 : 11 bytereg1bytereg2qwordregister2 to qwordregister10100 1R0B 0011 0011 : 11 qwordreg1qwordreg2memory to register0100 0RXB 0011 001w : mod reg r/mmemory8 to byteregister0100 0RXB 0011 0010 : mod bytereg r/mmemory64 to qwordregister0100 1RXB 0011 0011 : mod qwordreg r/mregister to memory0100 0RXB 0011 000w : mod reg r/mbyteregister to memory80100 0RXB 0011 0000 : mod bytereg r/mqwordregister to memory80100 1RXB 0011 0001 : mod qwordreg r/mimmediate to register0100 000B 1000 00sw : 11 110 reg : immimmediate8 to byteregister0100 000B 1000 0000 : 11 110 bytereg :imm8immediate32 to qwordregister0100 100B 1000 0001 : 11 110 qwordreg :imm32immediate8 to qwordregister0100 100B 1000 0011 : 11 110 qwordreg :imm8immediate to AL, AX, or EAX0100 000B 0011 010w : immimmediate to RAX0100 1000 0011 0101 : immediate dataimmediate to memory0100 00XB 1000 00sw : mod 110 r/m : immimmediate8 to memory80100 00XB 1000 0000 : mod 110 r/m : imm8immediate32 to memory640100 10XB 1000 0001 : mod 110 r/m : imm32immediate8 to memory640100 10XB 1000 0011 : mod 110 r/m : imm8Prefix Bytesaddress sizeB-52 Vol.
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