Volume 2B Instruction Set Reference N-Z (794102), страница 76
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2B B-75INSTRUCTION FORMATS AND ENCODINGSTable B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)Instruction and FormatEncodingSUBSD—Subtract Scalar DoublePrecision Floating-Point Valuesxmmreg to xmmreg1111 0010:0000 1111:0101 1100:11 xmmreg1xmmreg2mem to xmmreg1111 0010:0000 1111:0101 1100: mod xmmreg r/mUCOMISD—Unordered CompareScalar Ordered Double-PrecisionFloating-Point Values and SetEFLAGSxmmreg to xmmreg0110 0110:0000 1111:0010 1110:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:0010 1110: mod xmmreg r/mUNPCKHPD—Unpack and InterleaveHigh Packed Double-PrecisionFloating-Point Valuesxmmreg to xmmreg0110 0110:0000 1111:0001 0101:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:0001 0101: mod xmmreg r/mUNPCKLPD—Unpack and InterleaveLow Packed Double-PrecisionFloating-Point Valuesxmmreg to xmmreg0110 0110:0000 1111:0001 0100:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:0001 0100: mod xmmreg r/mXORPD—Bitwise Logical OR ofDouble-Precision Floating-PointValuesxmmreg to xmmreg0110 0110:0000 1111:0101 0111:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:0101 0111: mod xmmreg r/mB-76 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-26. Formats and Encodings of SSE2 Integer InstructionsInstruction and FormatEncodingMOVD—Move Doublewordreg to xmmeg0110 0110:0000 1111:0110 1110: 11 xmmreg regreg from xmmreg0110 0110:0000 1111:0111 1110: 11 xmmreg regmem to xmmreg0110 0110:0000 1111:0110 1110: mod xmmreg r/mmem from xmmreg0110 0110:0000 1111:0111 1110: mod xmmreg r/mMOVDQA—Move Aligned DoubleQuadwordxmmreg to xmmreg0110 0110:0000 1111:0110 1111:11 xmmreg1xmmreg20110 0110:0000 1111:0111 1111:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:0110 1111: mod xmmreg r/mmem from xmmreg0110 0110:0000 1111:0111 1111: mod xmmreg r/mMOVDQU—Move Unaligned DoubleQuadwordxmmreg to xmmreg1111 0011:0000 1111:0110 1111:11 xmmreg1xmmreg21111 0011:0000 1111:0111 1111:11 xmmreg1xmmreg2mem to xmmreg1111 0011:0000 1111:0110 1111: mod xmmreg r/mmem from xmmreg1111 0011:0000 1111:0111 1111: mod xmmreg r/mMOVQ2DQ—Move Quadword fromMMX to XMM Registermmreg to xmmreg1111 0011:0000 1111:1101 0110:11 mmreg1mmreg2MOVDQ2Q—Move Quadword fromXMM to MMX Registerxmmreg to mmreg1111 0010:0000 1111:1101 0110:11 mmreg1mmreg2MOVQ—Move Quadwordxmmreg2 to xmmreg11111 0011:0000 1111:0111 1110: 11 xmmreg1xmmreg2xmmreg2 from xmmreg10110 0110:0000 1111:1101 0110: 11 xmmreg1xmmreg2mem to xmmreg1111 0011:0000 1111:0111 1110: mod xmmreg r/mVol.
2B B-77INSTRUCTION FORMATS AND ENCODINGSTable B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.)Instruction and Formatmem from xmmregEncoding0110 0110:0000 1111:1101 0110: mod xmmreg r/m1PACKSSDW —Pack Dword To WordData (signed with saturation)xmmreg2 to xmmreg10110 0110:0000 1111:0110 1011: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111:0110 1011: mod xmmreg r/mPACKSSWB—Pack Word To Byte Data(signed with saturation)xmmreg2 to xmmreg10110 0110:0000 1111:0110 0011: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111:0110 0011: mod xmmreg r/mPACKUSWB—Pack Word To Byte Data(unsigned with saturation)xmmreg2 to xmmreg10110 0110:0000 1111:0110 0111: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111:0110 0111: mod xmmreg r/mPADDQ—Add Packed QuadwordIntegersmmreg to mmreg0000 1111:1101 0100:11 mmreg1 mmreg2mem to mmreg0000 1111:1101 0100: mod mmreg r/mxmmreg to xmmreg0110 0110:0000 1111:1101 0100:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:1101 0100: mod xmmreg r/mPADD—Add With Wrap-aroundxmmreg2 to xmmreg10110 0110:0000 1111: 1111 11gg: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111: 1111 11gg: mod xmmreg r/mPADDS—Add Signed With Saturationxmmreg2 to xmmreg10110 0110:0000 1111: 1110 11gg: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111: 1110 11gg: mod xmmreg r/mPADDUS—Add Unsigned WithSaturationxmmreg2 to xmmreg1B-78 Vol.
2B0110 0110:0000 1111: 1101 11gg: 11 xmmreg1xmmreg2INSTRUCTION FORMATS AND ENCODINGSTable B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.)Instruction and Formatmemory to xmmregEncoding0110 0110:0000 1111: 1101 11gg: mod xmmreg r/mPAND—Bitwise Andxmmreg2 to xmmreg10110 0110:0000 1111:1101 1011: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111:1101 1011: mod xmmreg r/mPANDN—Bitwise AndNotxmmreg2 to xmmreg10110 0110:0000 1111:1101 1111: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111:1101 1111: mod xmmreg r/mPAVGB—Average Packed Integersxmmreg to xmmreg0110 0110:0000 1111:11100 000:11 xmmreg1xmmreg2mem to xmmreg01100110:00001111:11100000 mod xmmreg r/mPAVGW—Average Packed Integersxmmreg to xmmreg0110 0110:0000 1111:1110 0011:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:1110 0011 mod xmmreg r/mPCMPEQ—Packed Compare ForEqualityxmmreg1 with xmmreg20110 0110:0000 1111:0111 01gg: 11 xmmreg1xmmreg2xmmreg with memory0110 0110:0000 1111:0111 01gg: mod xmmreg r/mPCMPGT—Packed Compare Greater(signed)xmmreg1 with xmmreg20110 0110:0000 1111:0110 01gg: 11 xmmreg1xmmreg2xmmreg with memory0110 0110:0000 1111:0110 01gg: mod xmmreg r/mPEXTRW—Extract Wordxmmreg to reg32, imm80110 0110:0000 1111:1100 0101:11 r32 xmmreg:imm8PINSRW—Insert Wordreg32 to xmmreg, imm80110 0110:0000 1111:1100 0100:11 xmmreg r32:imm8Vol.
2B B-79INSTRUCTION FORMATS AND ENCODINGSTable B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.)Instruction and Formatm16 to xmmreg, imm8Encoding0110 0110:0000 1111:1100 0100 mod xmmreg r/m:imm8PMADDWD—Packed Multiply Addxmmreg2 to xmmreg10110 0110:0000 1111:1111 0101: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111:1111 0101: mod xmmreg r/mPMAXSW—Maximum of PackedSigned Word Integersxmmreg to xmmreg0110 0110:0000 1111:1110 1110:11 xmmreg1xmmreg2mem to xmmreg01100110:00001111:11101110 mod xmmreg r/mPMAXUB—Maximum of PackedUnsigned Byte Integersxmmreg to xmmreg0110 0110:0000 1111:1101 1110:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:1101 1110 mod xmmreg r/mPMINSW—Minimum of Packed SignedWord Integersxmmreg to xmmreg0110 0110:0000 1111:1110 1010:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:1110 1010 mod xmmreg r/mPMINUB—Minimum of PackedUnsigned Byte Integersxmmreg to xmmreg0110 0110:0000 1111:1101 1010:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:1101 1010 mod xmmreg r/mPMOVMSKB—Move Byte Mask ToIntegerxmmreg to reg320110 0110:0000 1111:1101 0111:11 r32 xmmregPMULHUW—Packed multiplication,store high word (unsigned)xmmreg2 to xmmreg10110 0110:0000 1111:1110 0100: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111:1110 0100: mod xmmreg r/mB-80 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.)Instruction and FormatEncodingPMULHW—Packed Multiplication,store high wordxmmreg2 to xmmreg10110 0110:0000 1111:1110 0101: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111:1110 0101: mod xmmreg r/mPMULLW—Packed Multiplication,store low wordxmmreg2 to xmmreg10110 0110:0000 1111:1101 0101: 11 xmmreg1xmmreg2memory to xmmreg0110 0110:0000 1111:1101 0101: mod xmmreg r/mPMULUDQ—Multiply Packed UnsignedDoubleword Integersmmreg to mmreg0000 1111:1111 0100:11 mmreg1 mmreg2mem to mmreg0000 1111:1111 0100: mod mmreg r/mxmmreg to xmmreg0110 0110:00001111:1111 0100:11 xmmreg1xmmreg2mem to xmmreg0110 0110:00001111:1111 0100: mod xmmreg r/mPOR—Bitwise Orxmmreg2 to xmmreg10110 0110:0000 1111:1110 1011: 11 xmmreg1xmmreg2xmemory to xmmreg0110 0110:0000 1111:1110 1011: mod xmmreg r/mPSADBW—Compute Sum of AbsoluteDifferencesxmmreg to xmmreg0110 0110:0000 1111:1111 0110:11 xmmreg1xmmreg2mem to xmmreg0110 0110:0000 1111:1111 0110: mod xmmreg r/mPSHUFLW—Shuffle Packed LowWordsxmmreg to xmmreg, imm81111 0010:0000 1111:0111 0000:11 xmmreg1xmmreg2: imm8mem to xmmreg, imm81111 0010:0000 1111:0111 0000:11 mod xmmregr/m: imm8Vol.
2B B-81INSTRUCTION FORMATS AND ENCODINGSTable B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.)Instruction and FormatEncodingPSHUFHW—Shuffle Packed HighWordsxmmreg to xmmreg, imm81111 0011:0000 1111:0111 0000:11 xmmreg1xmmreg2: imm8mem to xmmreg, imm81111 0011:0000 1111:0111 0000:11 mod xmmregr/m: imm8PSHUFD—Shuffle PackedDoublewordsxmmreg to xmmreg, imm80110 0110:0000 1111:0111 0000:11 xmmreg1xmmreg2: imm8mem to xmmreg, imm80110 0110:0000 1111:0111 0000:11 mod xmmregr/m: imm8PSLLDQ—Shift Double Quadword LeftLogicalxmmreg, imm80110 0110:0000 1111:0111 0011:11 111 xmmreg:imm8PSLL—Packed Shift Left Logicalxmmreg1 by xmmreg20110 0110:0000 1111:1111 00gg: 11 xmmreg1xmmreg2xmmreg by memory0110 0110:0000 1111:1111 00gg: mod xmmreg r/mxmmreg by immediate0110 0110:0000 1111:0111 00gg: 11 110 xmmreg:imm8PSRA—Packed Shift Right Arithmeticxmmreg1 by xmmreg20110 0110:0000 1111:1110 00gg: 11 xmmreg1xmmreg2xmmreg by memory0110 0110:0000 1111:1110 00gg: mod xmmreg r/mxmmreg by immediate0110 0110:0000 1111:0111 00gg: 11 100 xmmreg:imm8PSRLDQ—Shift Double QuadwordRight Logicalxmmreg, imm80110 0110:00001111:01110011:11 011 xmmreg:imm8PSRL—Packed Shift Right Logicalxmmxreg1 by xmmxreg20110 0110:0000 1111:1101 00gg: 11 xmmreg1xmmreg2xmmxreg by memory0110 0110:0000 1111:1101 00gg: mod xmmreg r/mB-82 Vol.
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