Volume 2B Instruction Set Reference N-Z (794102), страница 79
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2BINSTRUCTION FORMATS AND ENCODINGSTable B-34. Floating-Point Instruction Formats and Encodings (Contd.)Instruction and FormatFLDZ – Load +0.0 into ST(0)Encoding11011 001 : 1110 1110FMUL – MultiplyST(0) ← ST(0) × 32-bit memory11011 000 : mod 001 r/mST(0) ← ST(0) × 64-bit memory11011 100 : mod 001 r/mST(d) ← ST(0) × ST(i)11011 d00 : 1100 1 ST(i)FMULP – MultiplyST(i) ← ST(0) × ST(i)11011 110 : 1100 1 ST(i)FNOP – No Operation11011 001 : 1101 0000FPATAN – Partial Arctangent11011 001 : 1111 0011FPREM – Partial Remainder11011 001 : 1111 1000FPREM1 – Partial Remainder (IEEE)11011 001 : 1111 0101FPTAN – Partial Tangent11011 001 : 1111 0010FRNDINT – Round to Integer11011 001 : 1111 1100FRSTOR – Restore FPU State11011 101 : mod 100 r/mFSAVE – Store FPU State11011 101 : mod 110 r/mFSCALE – Scale11011 001 : 1111 1101FSIN – Sine11011 001 : 1111 1110FSINCOS – Sine and Cosine11011 001 : 1111 1011FSQRT – Square Root11011 001 : 1111 1010FST – Store Real32-bit memory11011 001 : mod 010 r/m64-bit memory11011 101 : mod 010 r/mST(i)11011 101 : 11 010 ST(i)FSTCW – Store Control Word11011 001 : mod 111 r/mFSTENV – Store FPU Environment11011 001 : mod 110 r/mFSTP – Store Real and Pop32-bit memory11011 001 : mod 011 r/m64-bit memory11011 101 : mod 011 r/m80-bit memory11011 011 : mod 111 r/mST(i)FSTSW – Store Status Word into AX11011 101 : 11 011 ST(i)11011 111 : 1110 0000Vol.
2B B-99INSTRUCTION FORMATS AND ENCODINGSTable B-34. Floating-Point Instruction Formats and Encodings (Contd.)Instruction and FormatFSTSW – Store Status Word into MemoryEncoding11011 101 : mod 111 r/mFSUB – SubtractST(0) ← ST(0) – 32-bit memory11011 000 : mod 100 r/mST(0) ← ST(0) – 64-bit memory11011 100 : mod 100 r/mST(d) ← ST(0) – ST(i)11011 d00 : 1110 R ST(i)FSUBP – Subtract and PopST(0) ← ST(0) – ST(i)11011 110 : 1110 1 ST(i)FSUBR – Reverse SubtractST(0) ← 32-bit memory – ST(0)11011 000 : mod 101 r/mST(0) ← 64-bit memory – ST(0)11011 100 : mod 101 r/mST(d) ← ST(i) – ST(0)11011 d00 : 1110 R ST(i)FSUBRP – Reverse Subtract and PopST(i) ← ST(i) – ST(0)11011 110 : 1110 0 ST(i)FTST – Test11011 001 : 1110 0100FUCOM – Unordered Compare Real11011 101 : 1110 0 ST(i)FUCOMP – Unordered Compare Real and Pop11011 101 : 1110 1 ST(i)FUCOMPP – Unordered Compare Real and PopTwice11011 010 : 1110 1001FUCOMI – Unorderd Compare Real and SetEFLAGS11011 011 : 11 101 ST(i)FUCOMIP – Unorderd Compare Real, SetEFLAGS, and Pop11011 111 : 11 101 ST(i)FXAM – Examine11011 001 : 1110 0101FXCH – Exchange ST(0) and ST(i)11011 001 : 1100 1 ST(i)FXTRACT – Extract Exponent and Significand11011 001 : 1111 0100FYL2X – ST(1) × log2(ST(0))11011 001 : 1111 0001FYL2XP1 – ST(1) × log2(ST(0) + 1.0)11011 001 : 1111 1001FWAIT – Wait until FPU Ready1001 1011B-100 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSB.13VMX INSTRUCTIONSTable B-35 describes virtual-machine extensions (VMX).Table B-35. Encodings for VMX InstructionsInstruction and FormatEncodingVMCALL—Call to VM MonitorCall VMM: causes VM exit.00001111 00000001 11000001VMCLEAR—Clear Virtual-Machine ControlStructuremem32:VMCS_data_ptr01100110 00001111 11000111: mod 110 r/mmem64:VMCS_data_ptr01100110 00001111 11000111: mod 110 r/mVMLAUNCH—Launch Virtual MachineLaunch VM managed by Current_VMCS00001111 00000001 11000010VMRESUME—Resume Virtual MachineResume VM managed by Current_VMCS00001111 00000001 11000011VMPTRLD—Load Pointer to VirtualMachine Control Structuremem32 to Current_VMCS_ptr00001111 11000111: mod 110 r/mmem64 to Current_VMCS_ptr00001111 11000111: mod 110 r/mVMPTRST—Store Pointer to VirtualMachine Control StructureCurrent_VMCS_ptr to mem3200001111 11000111: mod 111 r/mCurrent_VMCS_ptr to mem6400001111 11000111: mod 111 r/mVMREAD—Read Field from Virtual-MachineControl Structurer32 (VMCS_fieldn) to r3200001111 01111000: 11 reg2 reg1r32 (VMCS_fieldn) to mem3200001111 01111000: mod r32 r/mr64 (VMCS_fieldn) to r6400001111 01111000: 11 reg2 reg1r64 (VMCS_fieldn) to mem6400001111 01111000: mod r64 r/mVMWRITE—Write Field to Virtual-MachineControl Structurer32 to r32 (VMCS_fieldn)00001111 01111001: 11 reg1 reg2mem32 to r32 (VMCS_fieldn)00001111 01111001: mod r32 r/mr64 to r64 (VMCS_fieldn)00001111 01111001: 11 reg1 reg2mem64 to r64 (VMCS_fieldn)00001111 01111001: mod r64 r/mVol.
2B B-101INSTRUCTION FORMATS AND ENCODINGSTable B-35. Encodings for VMX InstructionsInstruction and FormatEncodingVMXOFF—Leave VMX OperationLeave VMX.00001111 00000001 11000100VMXON—Enter VMX OperationEnter VMX.B-102 Vol. 2B11110011 000011111 11000111: mod 110 r/mAPPENDIX CINTEL® C/C++ COMPILER INTRINSICS ANDFUNCTIONAL EQUIVALENTSThe two tables in this appendix itemize the Intel C/C++ compiler intrinsics andfunctional equivalents for the Intel MMX technology, SSE, SSE2, SSE3, and SSSE3instructions.There may be additional intrinsics that do not have an instruction equivalent.
It isstrongly recommended that the reader reference the compiler documentation for thecomplete list of supported intrinsics. Please refer tohttp://www.intel.com/support/performancetools/.Table C-1 presents simple intrinsics and Table C-2 presents composite intrinsics.Some intrinsics are “composites” because they require more than one instruction toimplement them.Intel C/C++ Compiler intrinsic names reflect the following naming conventions:_mm_<intrin_op>_<suffix>where:<intrin_op>Indicates the intrinsics basic operation; for example, add foraddition and sub for subtraction<suffix>Denotes the type of data operated on by the instruction.
Thefirst one or two letters of each suffix denotes whether thedata is packed (p), extended packed (ep), or scalar (s).The remaining letters denote the type:ssingle-precision floating pointddouble-precision floating pointi128signed 128-bit integeri64signed 64-bit integeru64unsigned 64-bit integeri32signed 32-bit integeru32unsigned 32-bit integeri16signed 16-bit integeru16unsigned 16-bit integeri8signed 8-bit integeru8unsigned 8-bit integerThe variable r is generally used for the intrinsic's return value. A number appended toa variable name indicates the element of a packed object.
For example, r0 is thelowest word of r.Vol. 2B C-1INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTSThe packed values are represented in right-to-left order, with the lowest value beingused for scalar operations. Consider the following example operation:double a[2] = {1.0, 2.0};__m128d t = _mm_load_pd(a);The result is the same as either of the following:__m128d t = _mm_set_pd(2.0, 1.0);__m128d t = _mm_setr_pd(1.0, 2.0);In other words, the XMM register that holds the value t will look as follows:2.01271.064 630The “scalar” element is 1.0. Due to the nature of the instruction, some intrinsicsrequire their arguments to be immediates (constant integer literals).To use an intrinsic in your code, insert a line with the following syntax:data_type intrinsic_name (parameters)Where:data_typeIs the return data type, which can be either void, int,__m64, __m128, __m128d, or __m128i.
Only the_mm_empty intrinsic returns void.intrinsic_nameIs the name of the intrinsic, which behaves like a functionthat you can use in your C/C++ code instead of in-lining theactual instruction.parametersRepresents the parameters required by each intrinsic.C.1SIMPLE INTRINSICSNOTEFor detailed descriptions of the intrinsics in Table C-1, see the corresponding mnemonic in Chapter 3 in the “Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A”, or Chapter 4,“Instruction Set Reference, N-Z” in the “Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B”.C-2 Vol. 2BINTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTSTable C-1. Simple IntrinsicsMnemonicIntrinsicADDPD__m128d _mm_add_pd(__m128d a, __m128d b)ADDPS__m128 _mm_add_ps(__m128 a, __m128 b)ADDSD__m128d _mm_add_sd(__m128d a, __m128d b)ADDSS__m128 _mm_add_ss(__m128 a, __m128 b)ADDSUBPD__m128d _mm_addsub_pd(__m128d a, __m128d b)ADDSUBPS__m128 _mm_addsub_ps(__m128 a, __m128 b)ANDNPD__m128d _mm_andnot_pd(__m128d a, __m128d b)ANDNPS__m128 _mm_andnot_ps(__m128 a, __m128 b)ANDPD__m128d _mm_and_pd(__m128d a, __m128d b)ANDPS__m128 _mm_and_ps(__m128 a, __m128 b)CLFLUSHvoid _mm_clflush(void const *p)CMPPD__m128d _mm_cmpeq_pd(__m128d a, __m128d b)__m128d _mm_cmplt_pd(__m128d a, __m128d b)__m128d _mm_cmple_pd(__m128d a, __m128d b)__m128d _mm_cmpgt_pd(__m128d a, __m128d b)__m128d _mm_cmpge_pd(__m128d a, __m128d b)__m128d _mm_cmpneq_pd(__m128d a, __m128d b)__m128d _mm_cmpnlt_pd(__m128d a, __m128d b)__m128d _mm_cmpngt_pd(__m128d a, __m128d b)__m128d _mm_cmpnge_pd(__m128d a, __m128d b)__m128d _mm_cmpord_pd(__m128d a, __m128d b)__m128d _mm_cmpunord_pd(__m128d a, __m128d b)__m128d _mm_cmpnle_pd(__m128d a, __m128d b)CMPPS__m128 _mm_cmpeq_ps(__m128 a, __m128 b)__m128 _mm_cmplt_ps(__m128 a, __m128 b)__m128 _mm_cmple_ps(__m128 a, __m128 b)__m128 _mm_cmpgt_ps(__m128 a, __m128 b)__m128 _mm_cmpge_ps(__m128 a, __m128 b)__m128 _mm_cmpneq_ps(__m128 a, __m128 b)__m128 _mm_cmpnlt_ps(__m128 a, __m128 b)__m128 _mm_cmpngt_ps(__m128 a, __m128 b)__m128 _mm_cmpnge_ps(__m128 a, __m128 b)__m128 _mm_cmpord_ps(__m128 a, __m128 b)__m128 _mm_cmpunord_ps(__m128 a, __m128 b)__m128 _mm_cmpnle_ps(__m128 a, __m128 b)Vol.
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