Volume 2B Instruction Set Reference N-Z (794102), страница 83
Текст из файла (страница 83)
2B INDEX-5INDEX16-bit addressing forms, 2-632-bit addressing forms of, 2-7description of, 2-4MONITOR instruction, 3-596CPUID flag, 3-173feature data, 3-181MOV instruction, 3-599MOV instruction (control registers), 3-605MOV instruction (debug registers), 3-608MOVAPD instruction, 3-610MOVAPS instruction, 3-613MOVD instruction, 3-616MOVDDUP instruction, 3-620MOVDQ2Q instruction, 3-628MOVDQA instruction, 3-623MOVDQU instruction, 3-625MOVHLPS instruction, 3-630MOVHPD instruction, 3-632MOVHPS instruction, 3-635MOVLHP instruction, 3-638MOVLHPS instruction, 3-638MOVLPD instruction, 3-640MOVLPS instruction, 3-642MOVMSKPD instruction, 3-645MOVMSKPS instruction, 3-647MOVNTDQ instruction, 3-649MOVNTI instruction, 3-652MOVNTPD instruction, 3-654MOVNTPS instruction, 3-657MOVNTQ instruction, 3-660MOVQ instruction, 3-616, 3-663MOVQ2DQ instruction, 3-666MOVS instruction, 3-668, 4-255MOVSB instruction, 3-668MOVSD instruction, 3-668, 3-673MOVSHDUP instruction, 3-676MOVSLDUP instruction, 3-679MOVSQ instruction, 3-668MOVSS instruction, 3-682MOVSW instruction, 3-668MOVSX instruction, 3-685MOVSXD instruction, 3-685MOVUPD instruction, 3-687MOVUPS instruction, 3-690MOVZX instruction, 3-693MSRs (model specific registers)reading, 4-244MUL instruction, 3-23, 3-695MULPD instruction, 3-698MULPS instruction, 3-701MULSD instruction, 3-704MULSS instruction, 3-707Multi-byte no operation, 4-5, B-16MWAIT instruction, 3-710CPUID flag, 3-173feature data, 3-181INDEX-6 Vol.
2BNNaN. testing for, 3-406Nearreturn, RET instruction, 4-258NEG instruction, 3-549, 4-2NetBurst microarchitecture (see Intel NetBurstmicroarchitecture)No operation, 4-5, B-16Nomenclature, used in instruction reference pages,3-1NOP instruction, 4-5NOT instruction, 3-549, 4-7Notationbit and byte order, 1-3exceptions, 1-6hexadecimal and binary numbers, 1-5instruction operands, 1-5reserved bits, 1-4segmented addressing, 1-5Notational conventions, 1-3NT (nested task) flag, EFLAGS register, 3-490OOF (carry) flag, EFLAGS register, 3-458OF (overflow) flag, EFLAGS register, 3-30, 3-471,3-695, 4-288, 4-305, 4-308, 4-351Opcode format, 2-3Opcodesaddressing method codes for, A-2extensions, A-20extensions tables, A-21group numbers, A-20integersone-byte opcodes, A-10two-byte opcodes, A-10key to abbreviations, A-2look-up examples, A-4, A-20, A-23ModR/M byte, A-20one-byte opcodes, A-4, A-10opcode maps, A-1operand type codes for, A-3register codes for, A-4superscripts in tables, A-7two-byte opcodes, A-5, A-6, A-10VMX instructions, B-101x87 ESC instruction opcodes, A-23Operands, 1-5OR instruction, 3-549, 4-9ORPD instruction, 4-12ORPS instruction, 4-14OUT instruction, 4-16OUTS instruction, 4-18, 4-255OUTSB instruction, 4-18OUTSD instruction, 4-18OUTSW instruction, 4-18Overflow exception (#OF), 3-471INDEXPP6 family processorsdescription of, 1-1machine encodings, B-58PABSB instruction, 4-23PABSD instruction, 4-23PABSW instruction, 4-23PACKSSDW instruction, 4-27PACKSSWB instruction, 4-27PACKUSWB instruction, 4-32PADDB instruction, 4-36PADDD instruction, 4-36PADDQ instruction, 4-40PADDSB instruction, 4-43PADDSW instruction, 4-43PADDUSB instruction, 4-47PADDUSW instruction, 4-47PADDW instruction, 4-36PALIGNR instruction, 4-51PAND instruction, 4-54PANDN instruction, 4-57PAUSE instruction, 4-60PAVGB instruction, 4-61PAVGW instruction, 4-61PCE flag, CR4 register, 4-247PCMPEQB instruction, 4-64PCMPEQD instruction, 4-64PCMPEQW instruction, 4-64PCMPGTB instruction, 4-68PCMPGTD instruction, 4-68PCMPGTW instruction, 4-68PE (protection enable) flag, CR0 register, 3-547Pending break enable, 3-177Pentium 4 processor, 1-1Pentium II processor, 1-2Pentium III processor, 1-2Pentium Pro processor, 1-2Pentium processor, 1-1Pentium processor family processorsmachine encodings, B-53Performance-monitoring countersCPUID inquiry for, 3-181reading, 4-246PEXTRW instruction, 4-73PHADDD instruction, 4-76PHADDSW instruction, 4-79PHADDW instruction, 4-76PHSUBD instruction, 4-82PHSUBSW instruction, 4-85PHSUBW instruction, 4-82Pi, 3-344PINSRW instruction, 4-88, 4-168PMADDUBSW instruction, 4-91PMADDUDSW instruction, 4-91PMADDWD instruction, 4-94PMAXSW instruction, 4-98PMAXUB instruction, 4-101PMINSW instruction, 4-104PMINUB instruction, 4-107PMOVMSKB instruction, 4-110PMULHRSW instruction, 4-113PMULHUW instruction, 4-116PMULHW instruction, 4-120PMULLW instruction, 4-123PMULUDQ instruction, 4-127POP instruction, 4-130POPA instruction, 4-137POPAD instruction, 4-137POPF instruction, 4-139POPFD instruction, 4-139POPFQ instruction, 4-139POR instruction, 4-143PREFETCHh instruction, 4-146PrefixesAddress-size override prefix, 2-2Branch hints, 2-2branch hints, 2-2instruction, description of, 2-1legacy prefix encodings, B-2LOCK, 2-1, 3-549Operand-size override prefix, 2-2REP or REPE/REPZ, 2-2REPNE/REPNZ, 2-2REP/REPE/REPZ/REPNE/REPNZ, 4-253REX prefix encodings, B-2Segment override prefixes, 2-2PSADBW instruction, 4-148Pseudo-functionsVMfail, 5-2VMfailInvalid, 5-2VMfailValid, 5-2VMsucceed, 5-2PSHUFB instruction, 4-152PSHUFD instruction, 4-156PSHUFHW instruction, 4-159PSHUFLW instruction, 4-162PSHUFW instruction, 4-165PSIGNB instruction, 4-168PSIGND instruction, 4-168PSIGNW instruction, 4-168PSLLD instruction, 4-175PSLLDQ instruction, 4-173PSLLQ instruction, 4-175PSLLW instruction, 4-175PSRAD instruction, 4-180PSRAW instruction, 4-180PSRLD instruction, 4-187PSRLDQ instruction, 4-185PSRLQ instruction, 4-187PSRLW instruction, 4-187PSUBB instruction, 4-192PSUBD instruction, 4-192PSUBQ instruction, 4-196PSUBSB instruction, 4-199PSUBSW instruction, 4-199PSUBUSB instruction, 4-203Vol.
2B INDEX-7INDEXPSUBUSW instruction, 4-203PSUBW instruction, 4-192PUNPCKHBW instruction, 4-207PUNPCKHDQ instruction, 4-207PUNPCKHQDQ instruction, 4-207PUNPCKHWD instruction, 4-207PUNPCKLBW instruction, 4-212PUNPCKLDQ instruction, 4-212PUNPCKLQDQ instruction, 4-212PUNPCKLWD instruction, 4-212PUSH instruction, 4-217PUSHA instruction, 4-222PUSHAD instruction, 4-222PUSHF instruction, 4-225PUSHFD instruction, 4-225PXOR instruction, 4-228RRC (rounding control) field, x87 FPU control word,3-335, 3-344, 3-386RCL instruction, 4-231RCPPS instruction, 4-238RCPSS instruction, 4-241RCR instruction, 4-231RDMSR instruction, 4-244, 4-247, 4-251CPUID flag, 3-175RDPMC instruction, 4-246RDTSC instruction, 4-251Reg/opcode field, instruction format, 2-4Related literature, 1-7Remainder, x87 FPU operation, 3-362REP/REPE/REPZ/REPNE/REPNZ prefixes, 3-138,3-468, 4-19, 4-253Reserveduse of reserved bits, 1-4RET instruction, 4-258REX prefixesaddressing modes, 2-11and INC/DEC, 2-10encodings, 2-10, B-2field names, 2-11ModR/M byte, 2-10overview, 2-9REX.B, 2-10REX.R, 2-10REX.W, 2-10special encodings, 2-13RIP-relative addressing, 2-14ROL instruction, 4-231ROR instruction, 4-231Rounding, round to integer, x87 FPU operation, 3-368RPL field, 3-64RSM instruction, 4-270RSQRTPS instruction, 4-272RSQRTSS instruction, 4-275R/m field, instruction format, 2-4INDEX-8 Vol.
2BSSAHF instruction, 4-278SAL instruction, 4-280SAR instruction, 4-280SBB instruction, 3-549, 4-287Scale (operand addressing), 2-4Scale, x87 FPU operation, 3-377Scan string instructions, 4-291SCAS instruction, 4-255, 4-291SCASB instruction, 4-291SCASD instruction, 4-291SCASW instruction, 4-291Segmentdescriptor, segment limit, 3-558limit, 3-558registers, moving values to and from, 3-600selector, RPL field, 3-64Segmented addressing, 1-5Self Snoop, 3-177SETcc instructions, 4-296SF (sign) flag, EFLAGS register, 3-30SFENCE instruction, 4-301SGDT instruction, 4-302SHAF instruction, 4-278Shift instructions, 4-280SHL instruction, 4-280SHLD instruction, 4-305SHR instruction, 4-280SHRD instruction, 4-308SHUFPD instruction, 4-311SHUFPS instruction, 4-314SIB byte, 2-432-bit addressing forms of, 2-8description of, 2-4SIDT instruction, 4-302, 4-317Significand, extracting from floating-point number,3-429SIMD floating-point exceptions, unmasking, effectsof, 3-527Sine, x87 FPU operation, 3-379, 3-381SLDT instruction, 4-320SMSW instruction, 4-322SpeedStep technology, 3-173SQRTPD instruction, 4-325SQRTPS instruction, 4-328SQRTSD instruction, 4-331SQRTSS instruction, 4-334Square root, Fx87 PU operation, 3-384SS register, 3-529, 3-601, 4-131SSE extensionscacheability instruction encodings, B-67CPUID flag, 3-177floating-point encodings, B-59instruction encodings, B-59integer instruction encodings, B-66memory ordering encodings, B-67INDEXSSE2 extensionscacheability instruction encodings, B-84CPUID flag, 3-177floating-point encodings, B-69integer instruction encodings, B-77SSE3CPUID flag, 3-173SSE3 extensionsCPUID flag, 3-173event mgmt instruction encodings, B-86floating-point instruction encodings, B-85integer instruction encodings, B-86, B-87SSSE3 extensions, B-87CPUID flag, 3-173Stack, pushing values on, 4-218Status flags, EFLAGS register, 3-120, 3-123, 3-303,3-309, 3-505, 4-298, 4-380STC instruction, 4-337STD instruction, 4-338Stepping information, 3-180STI instruction, 4-339STMXCSR instruction, 4-342STOS instruction, 4-255, 4-344STOSB instruction, 4-344STOSD instruction, 4-344STOSQ instruction, 4-344STOSW instruction, 4-344STR instruction, 4-348String instructions, 3-136, 3-467, 3-551, 3-668,4-18, 4-291, 4-344SUB instruction, 3-25, 3-259, 3-549, 4-350SUBPD instruction, 4-353SUBSS instruction, 4-362Summary table notation, 3-7SWAPGS instruction, 4-365SYSCALL instruction, 4-367SYSENTER instruction, 4-369CPUID flag, 3-175SYSEXIT instruction, 4-373CPUID flag, 3-175SYSRET instruction, 4-377TTangent, x87 FPU operation, 3-365Task registerloading, 3-562storing, 4-348Task switchCALL instruction, 3-88return from nested task, IRET instruction, 3-490TEST instruction, 4-379Thermal MonitorCPUID flag, 3-177Thermal Monitor 2, 3-173CPUID flag, 3-173Time Stamp Counter, 3-175Time-stamp counter, reading, 4-251TLB entry, invalidating (flushing), 3-488TS (task switched) flag, CR0 register, 3-113TSD flag, CR4 register, 4-251TSS, relationship to task register, 4-348UUCOMISD instruction, 4-382UCOMISS instruction, 4-385UD2 instruction, 4-388Undefined, format opcodes, 3-406Unordered values, 3-305, 3-406, 3-408UNPCKHPD instruction, 4-389UNPCKHPS instruction, 4-392UNPCKLPD instruction, 4-395UNPCKLPS instruction, 4-398VVERR instruction, 4-401Version information, processor, 3-162VERW instruction, 4-401VM (virtual 8086 mode) flag, EFLAGS register, 3-490VMCALL instruction, 5-1VMCLEAR instruction, 5-1VMLAUNCH instruction, 5-1VMPTRLD instruction, 5-1VMPTRST instruction, 5-1VMREAD instruction, 5-1VMRESUME instruction, 5-1VMWRITE instruction, 5-1VMXOFF instruction, 5-1VMXON instruction, 5-2WWAIT/FWAIT instructions, 4-404WBINVD instruction, 4-406WBINVD/INVD bit, 3-164Write-back and invalidate caches, 4-406WRMSR instruction, 4-408CPUID flag, 3-175Xx87 FPUchecking for pending x87 FPU exceptions, 4-404constants, 3-344initialization, 3-332instruction opcodes, A-23x87 FPU control wordloading, 3-346, 3-348RC field, 3-335, 3-344, 3-386restoring, 3-370saving, 3-373, 3-392storing, 3-389x87 FPU data pointer, 3-348, 3-370, 3-373, 3-392x87 FPU instruction pointer, 3-348, 3-370, 3-373,3-392Vol.
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