Volume 2B Instruction Set Reference N-Z (794102), страница 78
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However, these entries are specialcases that do not follow the general rules (specified in Section B.4).Table B-32. Special Case Instructions Promoted Using REX.WInstruction and FormatEncodingCMOVcc—Conditional Moveregister2 to register10100 0R0B 0000 1111: 0100 tttn : 11 reg1reg2qwordregister2 to qwordregister10100 1R0B 0000 1111: 0100 tttn : 11qwordreg1 qwordreg2memory to register0100 0RXB 0000 1111 : 0100 tttn : mod regr/mmemory64 to qwordregister0100 1RXB 0000 1111 : 0100 tttn : modqwordreg r/mCVTSD2SI—Convert Scalar Double-PrecisionFloating-Point Value to Doubleword Integerxmmreg to r320100 0R0B 1111 0010:0000 1111:00101101:11 r32 xmmregxmmreg to r640100 1R0B 1111 0010:0000 1111:00101101:11 r64 xmmregmem64 to r320100 0R0XB 1111 0010:0000 1111:00101101: mod r32 r/mmem64 to r640100 1RXB 1111 0010:0000 1111:00101101: mod r64 r/mVol.
2B B-91INSTRUCTION FORMATS AND ENCODINGSTable B-32. Special Case Instructions Promoted Using REX.W (Contd.)Instruction and FormatEncodingCVTSI2SS—Convert Doubleword Integer toScalar Single-Precision Floating-Point Valuer32 to xmmreg10100 0R0B 1111 0011:0000 1111:00101010:11 xmmreg r32r64 to xmmreg10100 1R0B 1111 0011:0000 1111:00101010:11 xmmreg r64mem to xmmreg0100 0RXB 1111 0011:0000 1111:00101010: mod xmmreg r/mmem64 to xmmreg0100 1RXB 1111 0011:0000 1111:00101010: mod xmmreg r/mCVTSI2SD—Convert Doubleword Integer toScalar Double-Precision Floating-Point Valuer32 to xmmreg10100 0R0B 1111 0010:0000 1111:00101010:11 xmmreg r32r64 to xmmreg10100 1R0B 1111 0010:0000 1111:00101010:11 xmmreg r64mem to xmmreg0100 0RXB 1111 0010:0000 1111:00101010: mod xmmreg r/mmem64 to xmmreg0100 1RXB 1111 0010:0000 1111:00101010: mod xmmreg r/mCVTSS2SI—Convert Scalar Single-PrecisionFloating-Point Value to Doubleword Integerxmmreg to r320100 0R0B 1111 0011:0000 1111:00101101:11 r32 xmmregxmmreg to r640100 1R0B 1111 0011:0000 1111:00101101:11 r64 xmmregmem to r320100 0RXB 11110011:00001111:00101101:mod r32 r/mmem32 to r640100 1RXB 1111 0011:0000 1111:00101101: mod r64 r/mCVTTSD2SI—Convert with Truncation ScalarDouble-Precision Floating-Point Value toDoubleword Integerxmmreg to r32B-92 Vol.
2B0100 0R0B11110010:00001111:00101100:11 r32xmmregINSTRUCTION FORMATS AND ENCODINGSTable B-32. Special Case Instructions Promoted Using REX.W (Contd.)Instruction and FormatEncodingxmmreg to r640100 1R0B 1111 0010:0000 1111:00101100:11 r64 xmmregmem64 to r320100 0RXB 1111 0010:0000 1111:00101100: mod r32 r/mmem64 to r640100 1RXB 1111 0010:0000 1111:00101100: mod r64 r/mCVTTSS2SI—Convert with Truncation ScalarSingle-Precision Floating-Point Value toDoubleword Integerxmmreg to r320100 0R0B 1111 0011:0000 1111:00101100:11 r32 xmmreg1xmmreg to r640100 1R0B 1111 0011:0000 1111:00101100:11 r64 xmmreg1mem to r320100 0RXB 1111 0011:0000 1111:00101100: mod r32 r/mmem32 to r640100 1RXB 1111 0011:0000 1111:00101100: mod r64 r/mMOVD/MOVQ—Move doublewordreg to mmxreg0100 0R0B 0000 1111:0110 1110: 11mmxreg regqwordreg to mmxreg0100 1R0B 0000 1111:0110 1110: 11mmxreg qwordregreg from mmxreg0100 0R0B 0000 1111:0111 1110: 11mmxreg regqwordreg from mmxreg0100 1R0B 0000 1111:0111 1110: 11mmxreg qwordregmem to mmxreg0100 0RXB 0000 1111:0110 1110: modmmxreg r/mmem64 to mmxreg0100 1RXB 0000 1111:0110 1110: modmmxreg r/mmem from mmxreg0100 0RXB 0000 1111:0111 1110: modmmxreg r/mmem64 from mmxreg0100 1RXB 0000 1111:0111 1110: modmmxreg r/mmmxreg with memory0100 0RXB 0000 1111:0110 01gg: modmmxreg r/mVol.
2B B-93INSTRUCTION FORMATS AND ENCODINGSTable B-32. Special Case Instructions Promoted Using REX.W (Contd.)Instruction and FormatEncodingMOVMSKPS—Extract Packed Single-PrecisionFloating-Point Sign Maskxmmreg to r320100 0R0B 0000 1111:0101 0000:11 r32xmmregxmmreg to r640100 1R0B 00001111:01010000:11 r64xmmregPEXTRW—Extract Wordmmreg to reg32, imm80100 0R0B 0000 1111:1100 0101:11 r32mmreg: imm8mmreg to reg64, imm80100 1R0B 0000 1111:1100 0101:11 r64mmreg: imm8xmmreg to reg32, imm80100 0R0B 0110 0110 0000 1111:11000101:11 r32 xmmreg: imm8xmmreg to reg64, imm80100 1R0B 0110 0110 0000 1111:11000101:11 r64 xmmreg: imm8PINSRW—Insert Wordreg32 to mmreg, imm80100 0R0B 0000 1111:1100 0100:11 mmregr32: imm8reg64 to mmreg, imm80100 1R0B 0000 1111:1100 0100:11 mmregr64: imm8m16 to mmreg, imm80100 0R0B 0000 1111:1100 0100 modmmreg r/m: imm8m16 to mmreg, imm80100 1RXB 0000 1111:11000100 modmmreg r/m: imm8reg32 to xmmreg, imm80100 0RXB 0110 0110 0000 1111:11000100:11 xmmreg r32: imm8reg64 to xmmreg, imm80100 0RXB 0110 0110 0000 1111:11000100:11 xmmreg r64: imm8m16 to xmmreg, imm80100 0RXB 0110 0110 0000 1111:11000100 mod xmmreg r/m: imm8m16 to xmmreg, imm80100 1RXB 0110 0110 0000 1111:11000100 mod xmmreg r/m: imm8PMOVMSKB—Move Byte Mask To Integermmreg to reg32B-94 Vol.
2B0100 0RXB 0000 1111:1101 0111:11 r32mmregINSTRUCTION FORMATS AND ENCODINGSTable B-32. Special Case Instructions Promoted Using REX.W (Contd.)Instruction and FormatEncodingmmreg to reg640100 1R0B 0000 1111:1101 0111:11 r64mmregxmmreg to reg320100 0RXB 0110 0110 0000 1111:11010111:11 r32 mmregxmmreg to reg640110 0110 0000 1111:1101 0111:11 r64xmmregB.12FLOATING-POINT INSTRUCTION FORMATS ANDENCODINGSTable B-33 shows the five different formats used for floating-point instructions. In allcases, instructions are at least two bytes long and begin with the bit pattern 11011.Table B-33. General Floating-Point Instruction FormatsInstructionFirst ByteOPAOptional FieldsSecond Byte1110111211011311011dPOPA11OPB411011001111OP511011011111OP15–111098765MFmodOPAMF = Memory Format00 — 32-bit real01 — 32-bit integer10 — 64-bit real11 — 16-bit integerP = Pop0 — Do not pop stack1 — Pop stack after operationd = Destination0 — Destination is ST(0)1 — Destination is ST(i)1modOPBOPBR4r/ms-i-bdispr/ms-i-bdispST(i)32 1 0R XOR d = 0 — Destination OP SourceR XOR d = 1 — Source OP DestinationST(i) = Register stack element i000 = Stack Top001 = Second stack element⋅⋅⋅111 = Eighth stack elementThe Mod and R/M fields of the ModR/M byte have the same interpretation as thecorresponding fields of the integer instructions.
The SIB byte and disp (displace-Vol. 2B B-95INSTRUCTION FORMATS AND ENCODINGSment) are optionally present in instructions that have Mod and R/M fields. Their presence depends on the values of Mod and R/M, as for integer instructions.Table B-34 shows the formats and encodings of the floating-point instructions.Table B-34. Floating-Point Instruction Formats and EncodingsInstruction and FormatST(0)F2XM1 – Compute 2–1FABS – Absolute ValueEncoding11011 001 : 1111 000011011 001 : 1110 0001FADD – AddST(0) ← ST(0) + 32-bit memory11011 000 : mod 000 r/mST(0) ← ST(0) + 64-bit memory11011 100 : mod 000 r/mST(d) ← ST(0) + ST(i)11011 d00 : 11 000 ST(i)FADDP – Add and PopST(0) ← ST(0) + ST(i)11011 110 : 11 000 ST(i)FBLD – Load Binary Coded Decimal11011 111 : mod 100 r/mFBSTP – Store Binary Coded Decimal and Pop11011 111 : mod 110 r/mFCHS – Change Sign11011 001 : 1110 0000FCLEX – Clear Exceptions11011 011 : 1110 0010FCOM – Compare Real32-bit memory11011 000 : mod 010 r/m64-bit memory11011 100 : mod 010 r/mST(i)11011 000 : 11 010 ST(i)FCOMP – Compare Real and Pop32-bit memory11011 000 : mod 011 r/m64-bit memory11011 100 : mod 011 r/mST(i)11011 000 : 11 011 ST(i)FCOMPP – Compare Real and Pop Twice11011 110 : 11 011 001FCOMIP – Compare Real, Set EFLAGS, and Pop11011 111 : 11 110 ST(i)FCOS – Cosine of ST(0)11011 001 : 1111 1111FDECSTP – Decrement Stack-Top Pointer11011 001 : 1111 0110FDIV – DivideST(0) ← ST(0) ÷ 32-bit memory11011 000 : mod 110 r/mST(0) ← ST(0) ÷ 64-bit memory11011 100 : mod 110 r/mB-96 Vol.
2BINSTRUCTION FORMATS AND ENCODINGSTable B-34. Floating-Point Instruction Formats and Encodings (Contd.)Instruction and FormatST(d) ← ST(0) ÷ ST(i)Encoding11011 d00 : 1111 R ST(i)FDIVP – Divide and PopST(0) ← ST(0) ÷ ST(i)11011 110 : 1111 1 ST(i)FDIVR – Reverse DivideST(0) ← 32-bit memory ÷ ST(0)11011 000 : mod 111 r/mST(0) ← 64-bit memory ÷ ST(0)11011 100 : mod 111 r/mST(d) ← ST(i) ÷ ST(0)11011 d00 : 1111 R ST(i)FDIVRP – Reverse Divide and PopST(0) ¨ ST(i) ÷ ST(0)FFREE – Free ST(i) Register11011 110 : 1111 0 ST(i)11011 101 : 1100 0 ST(i)FIADD – Add IntegerST(0) ← ST(0) + 16-bit memory11011 110 : mod 000 r/mST(0) ← ST(0) + 32-bit memory11011 010 : mod 000 r/mFICOM – Compare Integer16-bit memory11011 110 : mod 010 r/m32-bit memory11011 010 : mod 010 r/mFICOMP – Compare Integer and Pop16-bit memory11011 110 : mod 011 r/m32-bit memory11011 010 : mod 011 r/mFIDIVST(0) ← ST(0) ÷ 16-bit memory11011 110 : mod 110 r/mST(0) ← ST(0) ÷ 32-bit memory11011 010 : mod 110 r/mFIDIVRST(0) ← 16-bit memory ÷ ST(0)11011 110 : mod 111 r/mST(0) ← 32-bit memory ÷ ST(0)11011 010 : mod 111 r/mFILD – Load Integer16-bit memory11011 111 : mod 000 r/m32-bit memory11011 011 : mod 000 r/m64-bit memory11011 111 : mod 101 r/mVol.
2B B-97INSTRUCTION FORMATS AND ENCODINGSTable B-34. Floating-Point Instruction Formats and Encodings (Contd.)Instruction and FormatEncodingFIMULST(0) ← ST(0) × 16-bit memory11011 110 : mod 001 r/mST(0) ← ST(0) × 32-bit memory11011 010 : mod 001 r/mFINCSTP – Increment Stack Pointer11011 001 : 1111 0111FINIT – Initialize Floating-Point UnitFIST – Store Integer16-bit memory11011 111 : mod 010 r/m32-bit memory11011 011 : mod 010 r/mFISTP – Store Integer and Pop16-bit memory11011 111 : mod 011 r/m32-bit memory11011 011 : mod 011 r/m64-bit memory11011 111 : mod 111 r/mFISUBST(0) ← ST(0) - 16-bit memory11011 110 : mod 100 r/mST(0) ← ST(0) - 32-bit memory11011 010 : mod 100 r/mFISUBRST(0) ← 16-bit memory − ST(0)11011 110 : mod 101 r/mST(0) ← 32-bit memory − ST(0)11011 010 : mod 101 r/mFLD – Load Real32-bit memory11011 001 : mod 000 r/m64-bit memory11011 101 : mod 000 r/m80-bit memory11011 011 : mod 101 r/mST(i)11011 001 : 11 000 ST(i)FLD1 – Load +1.0 into ST(0)11011 001 : 1110 1000FLDCW – Load Control Word11011 001 : mod 101 r/mFLDENV – Load FPU Environment11011 001 : mod 100 r/mFLDL2E – Load log2(ε) into ST(0)11011 001 : 1110 1010FLDL2T – Load log2(10) into ST(0)11011 001 : 1110 1001FLDLG2 – Load log10(2) into ST(0)11011 001 : 1110 1100FLDLN2 – Load logε(2) into ST(0)11011 001 : 1110 1101FLDPI – Load π into ST(0)11011 001 : 1110 1011B-98 Vol.
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