Volume 2B Instruction Set Reference N-Z (794102), страница 82
Текст из файла (страница 82)
2B INDEX-1INDEXsummary table notation, 3-7Compatibility, software, 1-4compilersdocumentation, 1-8Condition code flags, EFLAGS register, 3-116Condition code flags, x87 FPU status wordflags affected by instructions, 3-14setting, 3-406, 3-408, 3-411Conditional jump, 3-501Conforming code segment, 3-521Constants (floating point), loading, 3-344Control registers, moving values to and from, 3-605Cosine, x87 FPU operation, 3-312, 3-381CPL, 3-110, 4-401CPUID instruction, 3-162, 3-17636-bit page size extension, 3-176AP-485, 1-8APIC on-chip, 3-175basic CPUID information, 3-163cache and TLB characteristics, 3-163, 3-178CLFLUSH flag, 3-176CLFLUSH instruction cache line size, 3-171CMPXCHG16B flag, 3-173CMPXCHG8B flag, 3-175CPL qualified debug store, 3-173debug extensions, CR4.DE, 3-175debug store supported, 3-176deterministic cache parameters leaf, 3-164extended function information, 3-166feature information, 3-174FPU on-chip, 3-175FSAVE flag, 3-176FXRSTOR flag, 3-176HT technology flag, 3-177IA-32e mode available, 3-167input limits for EAX, 3-168L1 Context ID, 3-173local APIC physical ID, 3-171machine check architecture, 3-176machine check exception, 3-175memory type range registers, 3-175MONITOR feature information, 3-181MONITOR/MWAIT flag, 3-173MONITOR/MWAIT leaf, 3-165, 3-166MWAIT feature information, 3-181page attribute table, 3-176page size extension, 3-175performance monitoring features, 3-181physical address bits, 3-168physical address extension, 3-175power management, 3-181processor brand index, 3-171, 3-181processor brand string, 3-167, 3-181processor serial number, 3-163, 3-176processor type field, 3-170PTE global bit, 3-176RDMSR flag, 3-175returned in EBX, 3-171INDEX-2 Vol.
2Breturned in ECX & EDX, 3-172self snoop, 3-177SpeedStep technology, 3-173SS2 extensions flag, 3-177SSE extensions flag, 3-177SSE3 extensions flag, 3-173SSSE3 extensions flag, 3-173SYSENTER flag, 3-175SYSEXIT flag, 3-175thermal management, 3-181thermal monitor, 3-173, 3-176, 3-177time stamp counter, 3-175using CPUID, 3-162vendor ID string, 3-168version information, 3-163, 3-180virtual 8086 Mode flag, 3-175virtual address bits, 3-168WRMSR flag, 3-175CQO instruction, 3-255CR0 control register, 4-322CS register, 3-88, 3-471, 3-490, 3-509, 3-600, 4-131CVTDQ2PD instruction, 3-190CVTDQ2PS instruction, 3-192CVTPD2DQ instruction, 3-195CVTPD2PI instruction, 3-198CVTPD2PS instruction, 3-201CVTPI2PD instruction, 3-204CVTPI2PS instruction, 3-207CVTPS2DQ instruction, 3-210CVTPS2PD instruction, 3-213CVTPS2PI instruction, 3-216CVTSD2SI instruction, 3-219CVTSD2SS instruction, 3-222CVTSI2SD instruction, 3-225CVTSI2SS instruction, 3-228CVTSS2SD instruction, 3-231CVTSS2SI instruction, 3-234CVTTPD2DQ instruction, 3-240CVTTPD2PI instruction, 3-237CVTTPS2DQ instruction, 3-243CVTTPS2PI instruction, 3-246CVTTSD2SI instruction, 3-249CVTTSS2SI instruction, 3-252CWD instruction, 3-255CWDE instruction, 3-105C/C++ compiler intrinsicscompiler functional equivalents, C-1composite, C-14description of, 3-11lists of, C-1simple, C-2DD (default operation size) flag, segment descriptor,4-131, 4-137, 4-218DAA instruction, 3-257DAS instruction, 3-259INDEXDebug registers, moving value to and from, 3-608DEC instruction, 3-261, 3-549Denormalized finite number, 3-411DF (direction) flag, EFLAGS register, 3-107, 3-138,3-468, 3-552, 3-669, 4-19, 4-292, 4-338Displacement (operand addressing), 2-4DIV instruction, 3-264Divide error exception (#DE), 3-264DIVPD instruction, 3-268DIVPS instruction, 3-271DIVSD instruction, 3-274DIVSS instruction, 3-277DS register, 3-137, 3-529, 3-551, 3-668, 4-18EEDI register, 4-291, 4-338, 4-344Effective address, 3-535EFLAGS registercondition codes, 3-120, 3-303, 3-309flags affected by instructions, 3-14popping, 4-139popping on return from interrupt, 3-490pushing, 4-225pushing on interrupts, 3-471saving, 4-278status flags, 3-123, 3-505, 4-298, 4-380EIP register, 3-88, 3-471, 3-490, 3-509EMMS instruction, 3-280EncodingsSee machine instructions, opcodesENTER instruction, 3-282ES register, 3-529, 4-18, 4-291, 4-344ESI register, 3-137, 3-551, 3-552, 3-668, 4-18, 4-338ESP register, 3-88, 4-131ExceptionsBOUND range exceeded (#BR), 3-66notation, 1-6overflow exception (#OF), 3-471returning from, 3-490Exponent, extracting from floating-point number,3-429Extract exponent and significand, x87 FPUoperation, 3-429FF2XM1 instruction, 3-286, 3-429FABS instruction, 3-288FADD instruction, 3-290FADDP instruction, 3-290Far pointer, loading, 3-529Far return, RET instruction, 4-258FBLD instruction, 3-294FBSTP instruction, 3-296FCHS instruction, 3-299FCLEX instruction, 3-301FCMOVcc instructions, 3-303FCOM instruction, 3-305FCOMI instruction, 3-309FCOMIP instruction, 3-309FCOMP instruction, 3-305FCOMPP instruction, 3-305FCOS instruction, 3-312FDECSTP instruction, 3-314FDIV instruction, 3-316FDIVP instruction, 3-316FDIVR instruction, 3-320FDIVRP instruction, 3-320Feature information, processor, 3-162FFREE instruction, 3-324FIADD instruction, 3-290FICOM instruction, 3-325FICOMP instruction, 3-325FIDIV instruction, 3-316FIDIVR instruction, 3-320FILD instruction, 3-328FIMUL instruction, 3-351FINCSTP instruction, 3-330FINIT instruction, 3-332FINIT/FNINIT instructions, 3-373FIST instruction, 3-334FISTP instruction, 3-334FISTTP instruction, 3-338FISUB instruction, 3-398FISUBR instruction, 3-402FLD instruction, 3-341FLD1 instruction, 3-344FLDCW instruction, 3-346FLDENV instruction, 3-348FLDL2E instruction, 3-344FLDL2T instruction, 3-344FLDLG2 instruction, 3-344FLDLN2 instruction, 3-344FLDPI instruction, 3-344FLDZ instruction, 3-344Floating point instructionsmachine encodings, B-95Floating-point exceptionsSSE and SSE2 SIMD, 3-17x87 FPU, 3-17Flushingcaches, 3-486, 4-406TLB entry, 3-488FMUL instruction, 3-351FMULP instruction, 3-351FNCLEX instruction, 3-301FNINIT instruction, 3-332FNOP instruction, 3-355FNSAVE instruction, 3-373FNSTCW instruction, 3-389FNSTENV instruction, 3-348, 3-392FNSTSW instruction, 3-395FPATAN instruction, 3-356FPREM instruction, 3-359FPREM1 instruction, 3-362Vol.
2B INDEX-3INDEXFPTAN instruction, 3-365FRNDINT instruction, 3-368FRSTOR instruction, 3-370FS register, 3-529FSAVE instruction, 3-373FSAVE/FNSAVE instructions, 3-370FSCALE instruction, 3-377FSIN instruction, 3-379FSINCOS instruction, 3-381FSQRT instruction, 3-384FST instruction, 3-386FSTCW instruction, 3-389FSTENV instruction, 3-392FSTP instruction, 3-386FSTSW instruction, 3-395FSUB instruction, 3-398FSUBP instruction, 3-398FSUBR instruction, 3-402FSUBRP instruction, 3-402FTST instruction, 3-406FUCOM instruction, 3-408FUCOMI instruction, 3-309FUCOMIP instruction, 3-309FUCOMP instruction, 3-408FUCOMPP instruction, 3-408FXAM instruction, 3-411FXCH instruction, 3-413FXRSTOR instruction, 3-415CPUID flag, 3-176FXSAVE instruction, 3-418CPUID flag, 3-176FXTRACT instruction, 3-377, 3-429FYL2X instruction, 3-431FYL2XP1 instruction, 3-433GGDT (global descriptor table), 3-541, 3-544GDTR (global descriptor table register), 3-541, 4-302General-purpose instructions64-bit encodings, B-24non-64-bit encodings, B-9General-purpose registersmoving value to and from, 3-600popping all, 4-137pushing all, 4-222GS register, 3-529HHADDPD instruction, 3-435, 3-436HADDPS instruction, 3-439Hexadecimal numbers, 1-5HLT instruction, 3-443HSUBPD instruction, 3-445HSUBPS instruction, 3-449Hyper-Threading TechnologyCPUID flag, 3-177INDEX-4 Vol.
2BIIA-32e modeCPUID flag, 3-167introduction, 2-9see 64-bit modesee compatibility modeIA32_SYSENTER_CS MSR, 4-372, 4-375, 4-376IA32_SYSENTER_EIP MSR, 4-372IA32_SYSENTER_ESP MSR, 4-372IDIV instruction, 3-453IDT (interrupt descriptor table), 3-472, 3-541IDTR (interrupt descriptor table register), 3-541,4-317IF (interrupt enable) flag, EFLAGS register, 3-110,4-339Immediate operands, 2-4IMUL instruction, 3-457IN instruction, 3-462INC instruction, 3-464, 3-549Index (operand addressing), 2-4Initialization x87 FPU, 3-332INS instruction, 3-467, 4-255INSB instruction, 3-467INSD instruction, 3-467instruction encodings, B-87Instruction formatbase field, 2-4description of reference information, 3-1displacement, 2-4immediate, 2-4index field, 2-4Mod field, 2-4ModR/M byte, 2-4opcode, 2-3operands, 1-5prefixes, 2-1reg/opcode field, 2-4r/m field, 2-4scale field, 2-4SIB byte, 2-4See also: machine instructions, opcodesInstruction reference, nomenclature, 3-1Instruction set, reference, 3-1INSW instruction, 3-467INT 3 instruction, 3-471Integer, storing, x87 FPU data type, 3-334Intel 64 architecturedefinition of, 1-2instruction format, 2-1relation to IA-32, 1-2Intel developer link, 1-8Intel NetBurst microarchitecture, 1-2Intel software network link, 1-8Intel VTune Performance Analyzerrelated information, 1-8Intel Xeon processor, 1-1INDEXInter-privilege levelcall, CALL instruction, 3-88return, RET instruction, 4-258Interruptsinterrupt vector 4, 3-471returning from, 3-490software, 3-471INTn instruction, 3-471INTO instruction, 3-471Intrinsicscompiler functional equivalents, C-1composite, C-14description of, 3-11list of, C-1simple, C-2INVD instruction, 3-486INVLPG instruction, 3-488IOPL (I/O privilege level) field, EFLAGS register, 3-110,4-225, 4-339IRET instruction, 3-490IRETD instruction, 3-490JJcc instructions, 3-501JMP instruction, 3-508Jump operation, 3-508LL1 Context ID, 3-173LAHF instruction, 3-518LAR instruction, 3-520LDDQU instruction, 3-524LDMXCSR instruction, 3-527LDS instruction, 3-529LDT (local descriptor table), 3-544LDTR (local descriptor table register), 3-544, 4-320LEA instruction, 3-535LEAVE instruction, 3-538LES instruction, 3-529LFENCE instruction, 3-540LFS instruction, 3-529LGDT instruction, 3-541LGS instruction, 3-529LIDT instruction, 3-541LLDT instruction, 3-544LMSW instruction, 3-547Load effective address operation, 3-535LOCK prefix, 3-28, 3-31, 3-54, 3-78, 3-81, 3-84,3-150, 3-261, 3-464, 3-549, 4-2, 4-7,4-10, 4-288, 4-351, 4-410, 4-414, 4-419Locking operation, 3-549LODS instruction, 3-551, 4-255LODSB instruction, 3-551LODSD instruction, 3-551LODSQ instruction, 3-551LODSW instruction, 3-551Log epsilon, x87 FPU operation, 3-431Log (base 2), x87 FPU operation, 3-433LOOP instructions, 3-555LOOPcc instructions, 3-555LSL instruction, 3-558LSS instruction, 3-529LTR instruction, 3-562MMachine check architectureCPUID flag, 3-176description, 3-176Machine instructions64-bit mode, B-1condition test (tttn) field, B-7direction bit (d) field, B-8floating-point instruction encodings, B-95general description, B-1general-purpose encodings, B-9–B-53legacy prefixes, B-2MMX encodings, B-54–B-58opcode fields, B-2operand size (w) bit, B-5P6 family encodings, B-58Pentium processor family encodings, B-53reg (reg) field, B-3, B-4REX prefixes, B-2segment register (sreg) field, B-6sign-extend (s) bit, B-5SIMD 64-bit encodings, B-54special 64-bit encodings, B-91special fields, B-2special-purpose register (eee) field, B-6SSE encodings, B-59–B-68SSE2 encodings, B-68–B-84SSE3 encodings, B-85–B-87SSSE3 encodings, B-87–B-91VMX encodings, B-101–B-102See also: opcodesMachine status word, CR0 register, 3-547, 4-322MASKMOVDQU instruction, 3-565MASKMOVQ instruction, 3-568MAXPD instruction, 3-571MAXPS instruction, 3-574MAXSD instruction, 3-577MAXSS instruction, 3-580MFENCE instruction, 3-583MINPD instruction, 3-584MINPS instruction, 3-587MINSD instruction, 3-590MINSS instruction, 3-593MMX instructionsCPUID flag for technology, 3-176encodings, B-54Mod field, instruction format, 2-4Model & family information, 3-180ModR/M byte, 2-4Vol.
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