Volume 2A Instruction Set Reference A-M (794101), страница 82
Текст из файла (страница 82)
The other logical processors in the physical processor remain active, unlessthey are each individually halted by executing a HLT instruction.The HLT instruction is a privileged instruction. When the processor is running inprotected or virtual-8086 mode, the privilege level of a program or procedure mustbe 0 to execute the HLT instruction.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationEnter Halt state;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the current privilege level is not 0.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsNone.HLT—HaltVol. 2A 3-501INSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-502 Vol.
2AHLT—HaltINSTRUCTION SET REFERENCE, A-MHSUBPD—Packed Double-FP Horizontal SubtractOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F 7D /rHSUBPD xmm1,xmm2/m128AValidValidHorizontal subtract packeddouble-precision floatingpoint values fromxmm2/m128 to xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionThe HSUBPD instruction subtracts horizontally the packed DP FP numbers of bothoperands.Subtracts the double-precision floating-point value in the high quadword of the destination operand from the low quadword of the destination operand and stores theresult in the low quadword of the destination operand.Subtracts the double-precision floating-point value in the high quadword of thesource operand from the low quadword of the source operand and stores the result inthe high quadword of the destination operand.
See Figure 3-12.+68%3'[PP[PPP>@>@[PPP>@>@[PP[PPP>@[PPP>@[PP>@[PP>@5HVXOW[PP>@>@20Figure 3-12. HSUBPD—Packed Double-FP Horizontal SubtractHSUBPD—Packed Double-FP Horizontal SubtractVol. 2A 3-503INSTRUCTION SET REFERENCE, A-MIn 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).Operationxmm1[63:0] = xmm1[63:0] − xmm1[127:64];xmm1[127:64] = xmm2/m128[63:0] − xmm2/m128[127:64];Intel C/C++ Compiler Intrinsic EquivalentHSUBPD__m128d _mm_hsub_pd(__m128d a, __m128d b)ExceptionsWhen the source operand is a memory operand, the operand must be aligned on a16-byte boundary or a general-protection exception (#GP) will be generated.Numeric ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Real Address Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.3-504 Vol.
2AHSUBPD—Packed Double-FP Horizontal SubtractINSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Virtual 8086 Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.HSUBPD—Packed Double-FP Horizontal SubtractVol.
2A 3-505INSTRUCTION SET REFERENCE, A-M#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID feature flag SSE3 is 0.If the LOCK prefix is used.3-506 Vol. 2AHSUBPD—Packed Double-FP Horizontal SubtractINSTRUCTION SET REFERENCE, A-MHSUBPS—Packed Single-FP Horizontal SubtractOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF2 0F 7D /rHSUBPS xmm1,xmm2/m128AValidValidHorizontal subtract packedsingle-precision floatingpoint values fromxmm2/m128 to xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionSubtracts the single-precision floating-point value in the second dword of the destination operand from the first dword of the destination operand and stores the resultin the first dword of the destination operand.Subtracts the single-precision floating-point value in the fourth dword of the destination operand from the third dword of the destination operand and stores the result inthe second dword of the destination operand.Subtracts the single-precision floating-point value in the second dword of the sourceoperand from the first dword of the source operand and stores the result in the thirddword of the destination operand.Subtracts the single-precision floating-point value in the fourth dword of the sourceoperand from the third dword of the source operand and stores the result in thefourth dword of the destination operand.See Figure 3-13.HSUBPS—Packed Single-FP Horizontal SubtractVol.
2A 3-507INSTRUCTION SET REFERENCE, A-M+68%36[PP[PPP>@>@>@>@[PPP>@>@>@>@[PP[PPP>@[PPP>@[PPP>@[PPP>@[PP>@[PP>@[PP>@[PP>@>@>@>@5(68/7[PP>@20Figure 3-13. HSUBPS—Packed Single-FP Horizontal SubtractIn 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).Operationxmm1[31:0] = xmm1[31:0] − xmm1[63:32];xmm1[63:32] = xmm1[95:64] −xmm1[127:96];xmm1[95:64] = xmm2/m128[31:0] − xmm2/m128[63:32];xmm1[127:96] = xmm2/m128[95:64] − xmm2/m128[127:96];Intel C/C++ Compiler Intrinsic EquivalentHSUBPS__m128 _mm_hsub_ps(__m128 a, __m128 b)ExceptionsWhen the source operand is a memory operand, the operand must be aligned on a16-byte boundary or a general-protection exception (#GP) will be generated.3-508 Vol. 2AHSUBPS—Packed Single-FP Horizontal SubtractINSTRUCTION SET REFERENCE, A-MNumeric ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Real Address Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Virtual 8086 Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.HSUBPS—Packed Single-FP Horizontal SubtractVol.
2A 3-509INSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If the LOCK prefix is used.If CPUID.01H:ECX.SSE3[bit 0] = 0.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.3-510 Vol.
2AHSUBPS—Packed Single-FP Horizontal SubtractINSTRUCTION SET REFERENCE, A-MIDIV—Signed DivideOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF6 /7IDIV r/m8AValidValidSigned divide AX by r/m8,with result stored in: AL ←Quotient, AH ← Remainder.REX + F6 /7IDIV r/m8*AValidN.E.Signed divide AX by r/m8,with result stored in AL ←Quotient, AH ← Remainder.F7 /7IDIV r/m16AValidValidSigned divide DX:AX byr/m16, with result stored inAX ← Quotient, DX ←Remainder.F7 /7IDIV r/m32AValidValidSigned divide EDX:EAX byr/m32, with result stored inEAX ← Quotient, EDX ←Remainder.REX.W + F7 /7IDIV r/m64AValidN.E.Signed divide RDX:RAX byr/m64, with result stored inRAX ← Quotient, RDX ←Remainder.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r)NANANADescriptionDivides the (signed) value in the AX, DX:AX, or EDX:EAX (dividend) by the sourceoperand (divisor) and stores the result in the AX (AH:AL), DX:AX, or EDX:EAX registers.
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