Volume 2A Instruction Set Reference A-M (794101), страница 86

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2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.INSERTPS — Insert Packed Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MINT n/INTO/INT 3—Call to Interrupt ProcedureOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeCCINT 3AValidValidInterrupt 3—trap todebugger.CD ibINT imm8BValidValidInterrupt vector numberspecified by immediatebyte.CEINTOAInvalidValidInterrupt 4—if overflow flagis 1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANABimm8NANANADescriptionThe INT n instruction generates a call to the interrupt or exception handler specifiedwith the destination operand (see the section titled “Interrupts and Exceptions” inChapter 6 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 1).

The destination operand specifies an interrupt vector number from 0 to255, encoded as an 8-bit unsigned intermediate value. Each interrupt vector numberprovides an index to a gate descriptor in the IDT. The first 32 interrupt vectornumbers are reserved by Intel for system use. Some of these interrupts are used forinternally generated exceptions.The INT n instruction is the general mnemonic for executing a software-generatedcall to an interrupt handler. The INTO instruction is a special mnemonic for callingoverflow exception (#OF), interrupt vector number 4.

The overflow interrupt checksthe OF flag in the EFLAGS register and calls the overflow interrupt handler if the OFflag is set to 1.The INT 3 instruction generates a special one byte opcode (CC) that is intended forcalling the debug exception handler. (This one byte form is valuable because it can beused to replace the first byte of any instruction with a breakpoint, including other onebyte instructions, without over-writing other code).

To further support its function asa debug breakpoint, the interrupt generated with the CC opcode also differs from theregular software interrupts as follows:•Interrupt redirection does not happen when in VME mode; the interrupt ishandled by a protected-mode handler.•The virtual-8086 mode IOPL checks do not occur. The interrupt is taken withoutfaulting at any IOPL level.INT n/INTO/INT 3—Call to Interrupt ProcedureVol. 2A 3-533INSTRUCTION SET REFERENCE, A-MNote that the “normal” 2-byte opcode for INT 3 (CD03) does not have these specialfeatures.

Intel and Microsoft assemblers will not generate the CD03 opcode from anymnemonic, but this opcode can be created by direct numeric code definition or byself-modifying code.The action of the INT n instruction (including the INTO and INT 3 instructions) issimilar to that of a far call made with the CALL instruction. The primary difference isthat with the INT n instruction, the EFLAGS register is pushed onto the stack beforethe return address. (The return address is a far address consisting of the currentvalues of the CS and EIP registers.) Returns from interrupt procedures are handledwith the IRET instruction, which pops the EFLAGS information and return addressfrom the stack.The interrupt vector number specifies an interrupt descriptor in the interruptdescriptor table (IDT); that is, it provides index into the IDT. The selected interruptdescriptor in turn contains a pointer to an interrupt or exception handler procedure.In protected mode, the IDT contains an array of 8-byte descriptors, each of whichis an interrupt gate, trap gate, or task gate.

In real-address mode, the IDT is anarray of 4-byte far pointers (2-byte code segment selector and a 2-byte instructionpointer), each of which point directly to a procedure in the selected segment. (Notethat in real-address mode, the IDT is called the interrupt vector table, and itspointers are called interrupt vectors.)The following decision table indicates which action in the lower portion of the table istaken given the conditions in the upper portion of the table. Each Y in the lowersection of the decision table represents a procedure defined in the “Operation”section for this instruction (except #GP).Table 3-56.

Decision TablePE01111111VM–––––011IOPL––––––<3=3DPL/CPLRELATIONSHIP–DPL<CPL–DPL>CPLDPL=CPL or CDPL<CPL & NC––INTERRUPT TYPE–S/W––––––GATE TYPE––TaskTrap orInterruptTrap orInterruptTrap orInterruptTrap orInterruptTrap orInterruptREAL-ADDRESSMODEYYYYYYYYYYYYYPROTECTED-MODETRAP-ORINTERRUPT-GATEINTER-PRIVILEGELEVEL-INTERRUPTINTRA-PRIVILEGELEVEL-INTERRUPT3-534 Vol. 2AYYINT n/INTO/INT 3—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-MTable 3-56.

Decision Table (Contd.)INTERRUPT-FROMVIRTUAL-8086-MODEYTASK-GATE#GPYYYYNOTES:−Don't Care.YYes, action taken.Blank Action not taken.When the processor is executing in virtual-8086 mode, the IOPL determines theaction of the INT n instruction. If the IOPL is less than 3, the processor generates a#GP(selector) exception; if the IOPL is 3, the processor executes a protected modeinterrupt to privilege level 0. The interrupt gate's DPL must be set to 3 and the targetCPL of the interrupt handler procedure must be 0 to execute the protected modeinterrupt to privilege level 0.The interrupt descriptor table register (IDTR) specifies the base linear address andlimit of the IDT.

The initial base address value of the IDTR after the processor ispowered up or reset is 0.OperationThe following operational description applies not only to the INT n and INTO instructions, but also to external interrupts and exceptions.IF PE = 0THENGOTO REAL-ADDRESS-MODE;ELSE (* PE = 1 *)IF (VM = 1 and IOPL < 3 AND INT n)THEN#GP(0);ELSE (* Protected mode, IA-32e mode, or virtual-8086 mode interrupt *)IF (IA32_EFER.LMA = 0)THEN (* Protected mode, or virtual-8086 mode interrupt *)GOTO PROTECTED-MODE;ELSE (* IA-32e mode interrupt *)GOTO IA-32e-MODE;FI;FI;FI;REAL-ADDRESS-MODE:INT n/INTO/INT 3—Call to Interrupt ProcedureVol. 2A 3-535INSTRUCTION SET REFERENCE, A-MIF ((vector_number ∗ 4) + 3) is not within IDT limitTHEN #GP; FI;IF stack not large enough for a 6-byte return informationTHEN #SS; FI;Push (EFLAGS[15:0]);IF ← 0; (* Clear interrupt flag *)TF ← 0; (* Clear trap flag *)AC ← 0; (* Clear AC flag *)Push(CS);Push(IP);(* No error codes are pushed *)CS ← IDT(Descriptor (vector_number ∗ 4), selector));EIP ← IDT(Descriptor (vector_number ∗ 4), offset)); (* 16 bit offset AND 0000FFFFH *)END;PROTECTED-MODE:IF ((vector_number ∗ 8) + 7) is not within IDT limitsor selected IDT descriptor is not an interrupt-, trap-, or task-gate typeTHEN #GP((vector_number ∗ 8) + 2 + EXT); FI;(* EXT is bit 0 in error code *)IF software interrupt (* Generated by INT n, INT 3, or INTO *)THENIF gate descriptor DPL < CPLTHEN #GP((vector_number ∗ 8) + 2 ); FI;(* PE = 1, DPL<CPL, software interrupt *)FI;IF gate not presentTHEN #NP((vector_number ∗ 8) + 2 + EXT); FI;IF task gate (* Specified in the selected interrupt table descriptor *)THEN GOTO TASK-GATE;ELSE GOTO TRAP-OR-INTERRUPT-GATE; (* PE = 1, trap/interrupt gate *)FI;END;IA-32e-MODE:IF ((vector_number ∗ 16) + 15) is not in IDT limitsor selected IDT descriptor is not an interrupt-, or trap-gate typeTHEN #GP((vector_number « 3) + 2 + EXT);(* EXT is bit 0 in error code *)FI;IF software interrupt (* Generated by INT n, INT 3, but not INTO *)THENIF gate descriptor DPL < CPLTHEN #GP((vector_number « 3) + 2 );(* PE = 1, DPL < CPL, software interrupt *)3-536 Vol.

2AINT n/INTO/INT 3—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-MFI;ELSE (* Generated by INTO *)#UD;FI;IF gate not presentTHEN #NP((vector_number « 3) + 2 + EXT);FI;IF ((vector_number * 16)[IST] ≠ 0)NewRSP ← TSS[ISTx]; FI;GOTO TRAP-OR-INTERRUPT-GATE; (* Trap/interrupt gate *)END;TASK-GATE: (* PE = 1, task gate *)Read segment selector in task gate (IDT descriptor);IF local/global bit is set to localor index not within GDT limitsTHEN #GP(TSS selector); FI;Access TSS descriptor in GDT;IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001)THEN #GP(TSS selector); FI;IF TSS not presentTHEN #NP(TSS selector); FI;SWITCH-TASKS (with nesting) to TSS;IF interrupt caused by fault with error codeTHENIF stack limit does not allow push of error codeTHEN #SS(0); FI;Push(error code);FI;IF EIP not within code segment limitTHEN #GP(0); FI;END;TRAP-OR-INTERRUPT-GATE:Read segment selector for trap or interrupt gate (IDT descriptor);IF segment selector for code segment is NULLTHEN #GP(0H + EXT); FI; (* NULL selector with EXT flag set *)IF segment selector is not within its descriptor table limitsTHEN #GP(selector + EXT); FI;Read trap or interrupt handler descriptor;IF descriptor does not indicate a code segmentor code segment descriptor DPL > CPLTHEN #GP(selector + EXT); FI;IF trap or interrupt gate segment is not present,THEN #NP(selector + EXT); FI;INT n/INTO/INT 3—Call to Interrupt ProcedureVol.

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