Volume 2A Instruction Set Reference A-M (794101), страница 88
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2A 3-545INSTRUCTION SET REFERENCE, A-MIf the segment selector for a TSS has its local/global bit set forlocal.#SS(selector)If the SS register is being loaded and the segment pointed to ismarked not present.If pushing the return address, flags, error code, stack segmentpointer, or data segments exceeds the bounds of the stacksegment.#NP(selector)If code segment, interrupt-, trap-, or task gate, or TSS is notpresent.#TS(selector)If the RPL of the stack segment selector in the TSS is not equalto the DPL of the code segment being accessed by the interruptor trap gate.If DPL of the stack segment descriptor for the TSS’s stacksegment is not equal to the DPL of the code segment descriptorfor the interrupt or trap gate.If the stack segment selector in the TSS is NULL.If the stack segment for the TSS is not a writable data segment.If segment-selector index for stack segment is outsidedescriptor table limits.#PF(fault-code)If a page fault occurs.#BPIf the INT 3 instruction is executed.#OFIf the INTO instruction is executed and the OF flag is set.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#GP(0)If the instruction pointer in the 64-bit interrupt gate or 64-bittrap gate is non-canonical.#GP(selector)If the segment selector in the 64-bit interrupt or trap gate isNULL.If the interrupt vector number is outside the IDT limits.If the interrupt vector number points to a gate which is in noncanonical space.If the interrupt vector number points to a descriptor which is nota 64-bit interrupt gate or 64-bit trap gate.If the descriptor pointed to by the gate selector is outside thedescriptor table limit.If the descriptor pointed to by the gate selector is in non-canonical space.3-546 Vol.
2AINT n/INTO/INT 3—Call to Interrupt ProcedureINSTRUCTION SET REFERENCE, A-MIf the descriptor pointed to by the gate selector is not a codesegment.If the descriptor pointed to by the gate selector doesn’t have theL-bit set, or has both the L-bit and D-bit set.If the descriptor pointed to by the gate selector has DPL > CPL.#SS(0)If a push of the old EFLAGS, CS selector, EIP, or error code is innon-canonical space with no stack switch.#SS(selector)If a push of the old SS selector, ESP, EFLAGS, CS selector, EIP, orerror code is in non-canonical space on a stack switch (eitherCPL change or no-CPL with IST).#NP(selector)If the 64-bit interrupt-gate, 64-bit trap-gate, or code segment isnot present.#TS(selector)If an attempt to load RSP from the TSS causes an access to noncanonical space.If the RSP from the TSS is outside descriptor table limits.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.INT n/INTO/INT 3—Call to Interrupt ProcedureVol.
2A 3-547INSTRUCTION SET REFERENCE, A-MINVD—Invalidate Internal CachesOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 08INVDAValidValidFlush internal caches;initiate flushing of externalcaches.NOTES:* See the IA-32 Architecture Compatibility section below.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionInvalidates (flushes) the processor’s internal caches and issues a special-functionbus cycle that directs external caches to also flush themselves. Data held in internalcaches is not written back to main memory.After executing this instruction, the processor does not wait for the external cachesto complete their flushing operation before proceeding with instruction execution.
Itis the responsibility of hardware to respond to the cache flush signal.The INVD instruction is a privileged instruction. When the processor is running inprotected mode, the CPL of a program or procedure must be 0 to execute thisinstruction.Use this instruction with care. Data cached internally and not written back to mainmemory will be lost. Unless there is a specific requirement or benefit to flushingcaches without writing back modified cache lines (for example, testing or faultrecovery where cache coherency with main memory is not a concern), softwareshould use the WBINVD instruction.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityThe INVD instruction is implementation dependent; it may be implemented differently on different families of Intel 64 or IA-32 processors.
This instruction is notsupported on IA-32 processors earlier than the Intel486 processor.OperationFlush(InternalCaches);SignalFlush(ExternalCaches);Continue (* Continue execution *)3-548 Vol. 2AINVD—Invalidate Internal CachesINSTRUCTION SET REFERENCE, A-MFlags AffectedNone.Protected Mode Exceptions#GP(0)If the current privilege level is not 0.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)The INVD instruction cannot be executed in virtual-8086 mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.INVD—Invalidate Internal CachesVol.
2A 3-549INSTRUCTION SET REFERENCE, A-MINVLPG—Invalidate TLB EntryOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 01/7INVLPG mAValidValidInvalidate TLB Entry forpage that contains m.NOTES:* See the IA-32 Architecture Compatibility section below.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r)NANANADescriptionInvalidates (flushes) the translation lookaside buffer (TLB) entry specified with thesource operand.
The source operand is a memory address. The processor determinesthe page that contains that address and flushes the TLB entry for that page.The INVLPG instruction is a privileged instruction. When the processor is running inprotected mode, the CPL of a program or procedure must be 0 to execute thisinstruction.The INVLPG instruction normally flushes the TLB entry only for the specified page;however, in some cases, it flushes the entire TLB. See “MOV—Move to/from ControlRegisters” in this chapter for further information on operations that flush the TLB.This instruction’s operation is the same in all non-64-bit modes. It also operates thesame in 64-bit mode, except if the memory address is in non-canonical form.
In thiscase, INVLPG is the same as a NOP.IA-32 Architecture CompatibilityThe INVLPG instruction is implementation dependent, and its function may be implemented differently on different families of Intel 64 or IA-32 processors. This instruction is not supported on IA-32 processors earlier than the Intel486 processor.OperationFlush(RelevantTLBEntries);Continue; (* Continue execution *)Flags AffectedNone.3-550 Vol. 2AINVLPG—Invalidate TLB EntryINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)#UDIf the current privilege level is not 0.Operand is a register.If the LOCK prefix is used.Real-Address Mode Exceptions#UDOperand is a register.If the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)The INVLPG instruction cannot be executed at the virtual-8086mode.64-Bit Mode Exceptions#GP(0)If the current privilege level is not 0.#UDOperand is a register.If the LOCK prefix is used.INVLPG—Invalidate TLB EntryVol.
2A 3-551INSTRUCTION SET REFERENCE, A-MIRET/IRETD—Interrupt ReturnOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeCFIRETAValidValidInterrupt return (16-bitoperand size).CFIRETDAValidValidInterrupt return (32-bitoperand size).REX.W + CFIRETQAValidN.E.Interrupt return (64-bitoperand size).Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionReturns program control from an exception or interrupt handler to a program orprocedure that was interrupted by an exception, an external interrupt, or a softwaregenerated interrupt.
These instructions are also used to perform a return from anested task. (A nested task is created when a CALL instruction is used to initiate atask switch or when an interrupt or exception causes a task switch to an interrupt orexception handler.) See the section titled “Task Linking” in Chapter 7 of the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volume 3A.IRET and IRETD are mnemonics for the same opcode. The IRETD mnemonic (interrupt return double) is intended for use when returning from an interrupt when usingthe 32-bit operand size; however, most assemblers use the IRET mnemonic interchangeably for both operand sizes.In Real-Address Mode, the IRET instruction preforms a far return to the interruptedprogram or procedure.
During this operation, the processor pops the return instruction pointer, return code segment selector, and EFLAGS image from the stack to theEIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted program or procedure.In Protected Mode, the action of the IRET instruction depends on the settings of theNT (nested task) and VM flags in the EFLAGS register and the VM flag in the EFLAGSimage stored on the current stack. Depending on the setting of these flags, theprocessor performs the following types of interrupt returns:•••••Return from virtual-8086 mode.Return to virtual-8086 mode.Intra-privilege level return.Inter-privilege level return.Return from nested task (task switch).3-552 Vol. 2AIRET/IRETD—Interrupt ReturnINSTRUCTION SET REFERENCE, A-MIf the NT flag (EFLAGS register) is cleared, the IRET instruction performs a far returnfrom the interrupt procedure, without a task switch.
The code segment beingreturned to must be equally or less privileged than the interrupt handler routine (asindicated by the RPL field of the code segment selector popped from the stack).As with a real-address mode interrupt return, the IRET instruction pops the returninstruction pointer, return code segment selector, and EFLAGS image from the stackto the EIP, CS, and EFLAGS registers, respectively, and then resumes execution ofthe interrupted program or procedure. If the return is to another privilege level, theIRET instruction also pops the stack pointer and SS from the stack, before resumingprogram execution. If the return is to virtual-8086 mode, the processor also pops thedata segment registers from the stack.If the NT flag is set, the IRET instruction performs a task switch (return) from anested task (a task called with a CALL instruction, an interrupt, or an exception) backto the calling or interrupted task.
The updated state of the task executing the IRETinstruction is saved in its TSS. If the task is re-entered later, the code that follows theIRET instruction is executed.If the NT flag is set and the processor is in IA-32e mode, the IRET instruction causesa general protection exception.In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.Wprefix promotes operation to 64 bits (IRETQ). See the summary chart at the beginning of this section for encoding data and limits.See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 22 ofthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, formore information about the behavior of this instruction in VMX non-root operation.OperationIF PE = 0THENGOTO REAL-ADDRESS-MODE;ELSEIF (IA32_EFER.LMA = 0)THEN (* Protected mode *)GOTO PROTECTED-MODE;ELSE (* IA-32e mode *)GOTO IA-32e-MODE;FI;FI;REAL-ADDRESS-MODE;IF OperandSize = 32THENIF top 12 bytes of stack not within stack limitsTHEN #SS; FI;IRET/IRETD—Interrupt ReturnVol.
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