Volume 2A Instruction Set Reference A-M (794101), страница 84
Текст из файла (страница 84)
2AIMUL—Signed MultiplyINSTRUCTION SET REFERENCE, A-M#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.IMUL—Signed MultiplyVol.
2A 3-519INSTRUCTION SET REFERENCE, A-MIN—Input from PortOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeE4 ibIN AL, imm8AValidValidInput byte from imm8 I/Oport address into AL.E5 ibIN AX, imm8AValidValidInput word from imm8 I/Oport address into AX.E5 ibIN EAX, imm8AValidValidInput dword from imm8 I/Oport address into EAX.ECIN AL,DXBValidValidInput byte from I/O port inDX into AL.EDIN AX,DXBValidValidInput word from I/O port inDX into AX.EDIN EAX,DXBValidValidInput doubleword from I/Oport in DX into EAX.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4Aimm8NANANABNANANANADescriptionCopies the value from the I/O port specified with the second operand (sourceoperand) to the destination operand (first operand). The source operand can be abyte-immediate or the DX register; the destination operand can be register AL, AX,or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively).
Using the DX register as a source operand allows I/O port addresses from 0to 65,535 to be accessed; using a byte immediate allows I/O port addresses 0 to 255to be accessed.When accessing an 8-bit I/O port, the opcode determines the port size; whenaccessing a 16- and 32-bit I/O port, the operand-size attribute determines the portsize. At the machine code level, I/O instructions are shorter when accessing 8-bit I/Oports. Here, the upper eight bits of the port address will be 0.This instruction is only useful for accessing I/O ports located in the processor’s I/Oaddress space.
See Chapter 13, “Input/Output,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information on accessing I/Oports in the I/O address space.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.3-520 Vol. 2AIN—Input from PortINSTRUCTION SET REFERENCE, A-MOperationIF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)IF (Any I/O Permission Bit for I/O port being accessed = 1)THEN (* I/O operation is not allowed *)#GP(0);ELSE ( * I/O operation is allowed *)DEST ← SRC; (* Read from selected I/O port *)FI;ELSE (Real Mode or Protected Mode with CPL ≤ IOPL *)DEST ← SRC; (* Read from selected I/O port *)FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If the CPL is greater than (has less privilege) the I/O privilegelevel (IOPL) and any of the corresponding I/O permission bits inTSS for the I/O port being accessed is 1.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If any of the I/O permission bits in the TSS for the I/O port beingaccessed is 1.#PF(fault-code)If a page fault occurs.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#GP(0)If the CPL is greater than (has less privilege) the I/O privilegelevel (IOPL) and any of the corresponding I/O permission bits inTSS for the I/O port being accessed is 1.#UDIf the LOCK prefix is used.IN—Input from PortVol.
2A 3-521INSTRUCTION SET REFERENCE, A-MINC—Increment by 1OpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeFE /0INC r/m8AValidValidREX + FE /0INC r/m8*AValidN.E.Increment r/m byte by 1.FF /0INC r/m16AValidValidIncrement r/m word by 1.FF /0INC r/m32AValidValidIncrement r/m doublewordby 1.REX.W + FF /0INC r/m64AValidN.E.Increment r/m quadword by1.40+ rw**INC r16BN.E.ValidIncrement word register by1.40+ rdINC r32BN.E.ValidIncrement doublewordregister by 1.Increment r/m byte by 1.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.** 40H through 47H are REX prefixes in 64-bit mode.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r, w)NANANABreg (r, w)NANANADescriptionAdds 1 to the destination operand, while preserving the state of the CF flag.
Thedestination operand can be a register or a memory location. This instruction allows aloop counter to be updated without disturbing the CF flag. (Use a ADD instructionwith an immediate operand of 1 to perform an increment operation that does updatesthe CF flag.)This instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, INC r16 and INC r32 are not encodable (because opcodes 40Hthrough 47H are REX prefixes). Otherwise, the instruction’s 64-bit mode defaultoperation size is 32 bits.
Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.3-522 Vol. 2AINC—Increment by 1INSTRUCTION SET REFERENCE, A-MOperationDEST ← DEST + 1;AFlags AffectedThe CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to theresult.Protected Mode Exceptions#GP(0)If the destination operand is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULLsegment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.INC—Increment by 1Vol.
2A 3-523INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.3-524 Vol. 2AINC—Increment by 1INSTRUCTION SET REFERENCE, A-MINS/INSB/INSW/INSD—Input from Port to StringOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode6CINS m8, DXAValidValidInput byte from I/O portspecified in DX into memorylocation specified in ES:(E)DIor RDI.*6DINS m16, DXAValidValidInput word from I/O portspecified in DX into memorylocation specified in ES:(E)DIor RDI.16DINS m32, DXAValidValidInput doubleword from I/Oport specified in DX intomemory location specified inES:(E)DI or RDI.16CINSBAValidValidInput byte from I/O portspecified in DX into memorylocation specified withES:(E)DI or RDI.16DINSWAValidValidInput word from I/O portspecified in DX into memorylocation specified in ES:(E)DIor RDI.16DINSDAValidValidInput doubleword from I/Oport specified in DX intomemory location specified inES:(E)DI or RDI.1NOTES:* In 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) address sizes are supported.
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