Volume 2A Instruction Set Reference A-M (794101), страница 81
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If the ST(0) operand is outsideof its acceptable range, the result is undefined and software should not rely on anexception being generated. Under some circumstances exceptions may be generatedwhen ST(0) is out of range, but this behavior is implementation specific and notguaranteed.The following table shows the results obtained when taking the log epsilon of variousclasses of numbers, assuming that underflow does not occur.Table 3-54.
FYL2XP1 ResultsST(0)ST(1)−(1 − ( 2 ⁄ 2 )) to −0-0+0+0 to +(1 - ( 2 ⁄ 2 ))NaN-•+•**-•NaN-F+F+0-0-FNaN-0+0+0-0-0NaN+0-0-0+0+0NaN+F-F-0+0+FNaN+•-•**+•NaNNaNNaNNaNNaNNaNNaNNOTES:F Means finite floating-point value.* Indicates floating-point invalid-operation (#IA) exception.This instruction provides optimal accuracy for values of epsilon [the value in registerST(0)] that are close to 0. For small epsilon (ε) values, more significant digits can beretained by using the FYL2XP1 instruction than by using (ε+1) as an argument to theFYL2X instruction. The (ε+1) expression is commonly found in compound interest andannuity calculations. The result can be simply converted into a value in another logarithm base by including a scale factor in the ST(1) source operand.
The followingFYL2XP1—Compute y * log2(x +1)Vol. 2A 3-491INSTRUCTION SET REFERENCE, A-Mequation is used to calculate the scale factor for a particular logarithm base, where nis the logarithm base desired for the result of the FYL2XP1 instruction:scale factor ← logn 2This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationST(1) ← ST(1) ∗ log2(ST(0) + 1.0);PopRegisterStack;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAEither operand is an SNaN value or unsupported format.#DSource operand is a denormal value.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-492 Vol.
2AFYL2XP1—Compute y * log2(x +1)INSTRUCTION SET REFERENCE, A-MHADDPD—Packed Double-FP Horizontal AddOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F 7C /rHADDPD xmm1,xmm2/m128AValidValidHorizontal add packeddouble-precision floatingpoint values fromxmm2/m128 to xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionAdds the double-precision floating-point values in the high and low quadwords of thedestination operand and stores the result in the low quadword of the destinationoperand.Adds the double-precision floating-point values in the high and low quadwords of thesource operand and stores the result in the high quadword of the destination operand.See Figure 3-10.+$''3'[PP[PPP>@>@[PPP>@>@[PP[PPP>@[PPP>@[PP>@[PP>@5HVXOW[PP>@>@20Figure 3-10.
HADDPD—Packed Double-FP Horizontal AddHADDPD—Packed Double-FP Horizontal AddVol. 2A 3-493INSTRUCTION SET REFERENCE, A-MIn 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).Operationxmm1[63:0] = xmm1[63:0] + xmm1[127:64];xmm1[127:64] = xmm2/m128[63:0] + xmm2/m128[127:64];Intel C/C++ Compiler Intrinsic EquivalentHADDPD__m128d _mm_hadd_pd(__m128d a, __m128d b)ExceptionsWhen the source operand is a memory operand, the operand must be aligned on a16-byte boundary or a general-protection exception (#GP) will be generated.Numeric ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Real Address Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.3-494 Vol.
2AHADDPD—Packed Double-FP Horizontal AddINSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Virtual 8086 Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.HADDPD—Packed Double-FP Horizontal AddVol.
2A 3-495INSTRUCTION SET REFERENCE, A-M#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID feature flag SSE3 is 0.If the LOCK prefix is used.3-496 Vol. 2AHADDPD—Packed Double-FP Horizontal AddINSTRUCTION SET REFERENCE, A-MHADDPS—Packed Single-FP Horizontal AddOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF2 0F 7C /rHADDPS xmm1,xmm2/m128AValidValidHorizontal add packedsingle-precision floatingpoint values fromxmm2/m128 to xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionAdds the single-precision floating-point values in the first and second dwords of thedestination operand and stores the result in the first dword of the destinationoperand.Adds single-precision floating-point values in the third and fourth dword of the destination operand and stores the result in the second dword of the destination operand.Adds single-precision floating-point values in the first and second dword of thesource operand and stores the result in the third dword of the destination operand.HADDPS—Packed Single-FP Horizontal AddVol.
2A 3-497INSTRUCTION SET REFERENCE, A-MAdds single-precision floating-point values in the third and fourth dword of the sourceoperand and stores the result in the fourth dword of the destination operand. SeeFigure 3-11.+$''36[PP[PPP>@>@>@>@[PPP>@>@>@>@[PP[PPP>@[PPP>@[PPP>@[PPP>@[PP>@[PP>@[PP>@[PP>@>@>@>@5(68/7[PP>@20Figure 3-11. HADDPS—Packed Single-FP Horizontal AddIn 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).Operationxmm1[31:0] = xmm1[31:0] + xmm1[63:32];xmm1[63:32] = xmm1[95:64] + xmm1[127:96];xmm1[95:64] = xmm2/m128[31:0] + xmm2/m128[63:32];xmm1[127:96] = xmm2/m128[95:64] + xmm2/m128[127:96];Intel C/C++ Compiler Intrinsic EquivalentHADDPS__m128 _mm_hadd_ps(__m128 a, __m128 b)3-498 Vol. 2AHADDPS—Packed Single-FP Horizontal AddINSTRUCTION SET REFERENCE, A-MExceptionsWhen the source operand is a memory operand, the operand must be aligned on a16-byte boundary or a general-protection exception (#GP) will be generated.Numeric ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Real Address Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.HADDPS—Packed Single-FP Horizontal AddVol.
2A 3-499INSTRUCTION SET REFERENCE, A-MVirtual 8086 Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1).#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID feature flag SSE3 is 0.If the LOCK prefix is used.3-500 Vol.
2AHADDPS—Packed Single-FP Horizontal AddINSTRUCTION SET REFERENCE, A-MHLT—HaltOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF4HLTAValidValidHaltInstruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionStops instruction execution and places the processor in a HALT state. An enabledinterrupt (including NMI and SMI), a debug exception, the BINIT# signal, the INIT#signal, or the RESET# signal will resume execution. If an interrupt (including NMI) isused to resume execution after a HLT instruction, the saved instruction pointer(CS:EIP) points to the instruction following the HLT instruction.When a HLT instruction is executed on an Intel 64 or IA-32 processor supporting IntelHyper-Threading Technology, only the logical processor that executes the instructionis halted.
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