Volume 2A Instruction Set Reference A-M (794101), страница 79
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If the alignment checkexception (#AC) is enabled (and the CPL is 3), signaling of #ACis not guaranteed and may vary with implementation, asfollows. In all implementations where #AC is not signaled, ageneral protection exception is signaled in its place. In addition,If CR0.EM[bit 2] = 1.If instruction is preceded by a LOCK prefix.3-474 Vol. 2AFXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR StateINSTRUCTION SET REFERENCE, A-Mthe width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignmentcheck exception might be signaled for a 2-byte misalignment,whereas a general protection exception might be signaled for allother misalignments (4-, 8-, or 16-byte misalignments).FXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR StateVol.
2A 3-475INSTRUCTION SET REFERENCE, A-MFXSAVE—Save x87 FPU, MMX Technology, and SSE StateOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F AE /0FXSAVEm512byteAValidValidSave the x87 FPU, MMX,XMM, and MXCSR registerstate to m512byte.REX.W+ 0F AE/0FXSAVE64m512byteAValidN.E.Save the x87 FPU, MMX,XMM, and MXCSR registerstate to m512byte.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (w)NANANADescriptionSaves the current state of the x87 FPU, MMX technology, XMM, and MXCSR registersto a 512-byte memory location specified in the destination operand.
The contentlayout of the 512 byte region depends on whether the processor is operating in non64-bit operating modes or 64-bit sub-mode of IA-32e mode.Bytes 464:511 are available to software use. The processor does not write to bytes464:511 of an FXSAVE area.The operation of FXSAVE in non-64-bit modes is described first.Non-64-Bit Mode OperationTable 3-48 shows the layout of the state information in memory when the processoris operating in legacy modes.Table 3-48.
Non-64-bit-Mode Layout of FXSAVE and FXRSTORMemory Region1514 13Rsrvd12CSMXCSR_MASK11 10987654FPU IPFOPRs FTWrvdMXCSRRsrvdDS32FSW10FCWFPU DP016ReservedST0/MM032ReservedST1/MM148ReservedST2/MM264ReservedST3/MM380ReservedST4/MM4963-476 Vol. 2AFXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-MTable 3-48. Non-64-bit-Mode Layout of FXSAVE and FXRSTORMemory Region (Contd.)1514 131211 109876543210ReservedST5/MM5112ReservedST6/MM6128ReservedST7/MM7144XMM0160XMM1176XMM2192XMM3208XMM4224XMM5240XMM6256XMM7272Reserved288Reserved304Reserved320Reserved336Reserved352Reserved368Reserved384Reserved400Reserved416Reserved432Reserved448Available464Available480Available496The destination operand contains the first byte of the memory image, and it must bealigned on a 16-byte boundary.
A misaligned destination operand will result in ageneral-protection (#GP) exception being generated (or in some cases, an alignmentcheck exception [#AC]).FXSAVE—Save x87 FPU, MMX Technology, and SSE StateVol. 2A 3-477INSTRUCTION SET REFERENCE, A-MThe FXSAVE instruction is used when an operating system needs to perform acontext switch or when an exception handler needs to save and examine the currentstate of the x87 FPU, MMX technology, and/or XMM and MXCSR registers.The fields in Table 3-48 are defined in Table 3-49.Table 3-49. Field DefinitionsFieldDefinitionFCWx87 FPU Control Word (16 bits).
See Figure 8-6 in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 1, for the layout ofthe x87 FPU control word.FSWx87 FPU Status Word (16 bits). See Figure 8-4 in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 1, for the layout ofthe x87 FPU status word.Abridged FTWx87 FPU Tag Word (8 bits).
The tag information saved here is abridged, asdescribed in the following paragraphs.FOPx87 FPU Opcode (16 bits). The lower 11 bits of this field contain theopcode, upper 5 bits are reserved. See Figure 8-8 in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 1, for the layout ofthe x87 FPU opcode field.FPU IPx87 FPU Instruction Pointer Offset (32 bits). The contents of this fielddiffer depending on the current addressing mode (32-bit or 16-bit) of theprocessor when the FXSAVE instruction was executed:32-bit mode — 32-bit IP offset.16-bit mode — low 16 bits are IP offset; high 16 bits are reserved.See “x87 FPU Instruction and Operand (Data) Pointers” in Chapter 8 of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,for a description of the x87 FPU instruction pointer.CSx87 FPU Instruction Pointer Selector (16 bits).FPU DPx87 FPU Instruction Operand (Data) Pointer Offset (32 bits).
The contentsof this field differ depending on the current addressing mode (32-bit or 16bit) of the processor when the FXSAVE instruction was executed:32-bit mode — 32-bit IP offset.16-bit mode — low 16 bits are IP offset; high 16 bits are reserved.See “x87 FPU Instruction and Operand (Data) Pointers” in Chapter 8 of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,for a description of the x87 FPU operand pointer.DS3-478 Vol. 2Ax87 FPU Instruction Operand (Data) Pointer Selector (16 bits).FXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-MTable 3-49.
Field Definitions (Contd.)FieldDefinitionMXCSRMXCSR Register State (32 bits). See Figure 10-3 in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 1, for the layout ofthe MXCSR register. If the OSFXSR bit in control register CR4 is not set, theFXSAVE instruction may not save this register. This behavior isimplementation dependent.MXCSR_MASKMXCSR_MASK (32 bits).
This mask can be used to adjust values written tothe MXCSR register, ensuring that reserved bits are set to 0. Set the maskbits and flags in MXCSR to the mode of operation desired for SSE and SSE2SIMD floating-point instructions. See “Guidelines for Writing to the MXCSRRegister” in Chapter 11 of the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 1, for instructions for how to determine anduse the MXCSR_MASK value.ST0/MM0 throughST7/MM7x87 FPU or MMX technology registers. These 80-bit fields contain the x87FPU data registers or the MMX technology registers, depending on thestate of the processor prior to the execution of the FXSAVE instruction.
Ifthe processor had been executing x87 FPU instruction prior to the FXSAVEinstruction, the x87 FPU data registers are saved; if it had been executingMMX instructions (or SSE or SSE2 instructions that operated on the MMXtechnology registers), the MMX technology registers are saved. When theMMX technology registers are saved, the high 16 bits of the field arereserved.XMM0 throughXMM7XMM registers (128 bits per field). If the OSFXSR bit in control register CR4is not set, the FXSAVE instruction may not save these registers.
Thisbehavior is implementation dependent.The FXSAVE instruction saves an abridged version of the x87 FPU tag word in theFTW field (unlike the FSAVE instruction, which saves the complete tag word). The taginformation is saved in physical register order (R0 through R7), rather than in top-ofstack (TOS) order.
With the FXSAVE instruction, however, only a single bit (1 for validor 0 for empty) is saved for each tag. For example, assume that the tag word iscurrently set as follows:R7 R6 R5 R4 R3 R2 R1 R011 xx xx xx 11 11 11 11Here, 11B indicates empty stack elements and “xx” indicates valid (00B), zero (01B),or special (10B).For this example, the FXSAVE instruction saves only the following 8 bits of information:R7 R6 R5 R4 R3 R2 R1 R00 1 1 1 0 0 0 0FXSAVE—Save x87 FPU, MMX Technology, and SSE StateVol. 2A 3-479INSTRUCTION SET REFERENCE, A-MHere, a 1 is saved for any valid, zero, or special tag, and a 0 is saved for any emptytag.The operation of the FXSAVE instruction differs from that of the FSAVE instruction,the as follows:•FXSAVE instruction does not check for pending unmasked floating-pointexceptions.
(The FXSAVE operation in this regard is similar to the operation of theFNSAVE instruction).•After the FXSAVE instruction has saved the state of the x87 FPU, MMXtechnology, XMM, and MXCSR registers, the processor retains the contents of theregisters. Because of this behavior, the FXSAVE instruction cannot be used by anapplication program to pass a “clean” x87 FPU state to a procedure, since itretains the current state. To clean the x87 FPU state, an application mustexplicitly execute an FINIT instruction after an FXSAVE instruction to reinitializethe x87 FPU state.•The format of the memory image saved with the FXSAVE instruction is the sameregardless of the current addressing mode (32-bit or 16-bit) and operating mode(protected, real address, or system management).
This behavior differs from theFSAVE instructions, where the memory image format is different depending onthe addressing mode and operating mode. Because of the different imageformats, the memory image saved with the FXSAVE instruction cannot berestored correctly with the FRSTOR instruction, and likewise the state saved withthe FSAVE instruction cannot be restored correctly with the FXRSTOR instruction.The FSAVE format for FTW can be recreated from the FTW valid bits and the stored80-bit FP data (assuming the stored data was not the contents of MMX technologyregisters) using Table 3-50.Table 3-50. Recreating FSAVE FormatExponentall 1’sExponentall 0’sFractionall 0’sJ and MbitsFTW validbitx87 FTW0000x1Special100001x1Valid00001001Special10001101Valid000100x1Special100101x1Special10011001Zero01011101Special101001x1Special101001x1Special103-480 Vol.
2AFXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-MTable 3-50. Recreating FSAVE Format (Contd.)Exponentall 1’sExponentall 0’sFractionall 0’sJ and MbitsFTW validbitx87 FTW101001Special10101101Special100Empty11For all legal combinations above.The J-bit is defined to be the 1-bit binary integer to the left of the decimal place in thesignificand. The M-bit is defined to be the most significant bit of the fractional portionof the significand (i.e., the bit immediately to the right of the decimal place).When the M-bit is the most significant bit of the fractional portion of the significand,it must be 0 if the fraction is all 0’s.IA-32e Mode OperationIn compatibility sub-mode of IA-32e mode, legacy SSE registers, XMM0 throughXMM7, are saved according to the legacy FXSAVE map.
In 64-bit mode, all of the SSEregisters, XMM0 through XMM15, are saved. Additionally, there are two differentlayouts of the FXSAVE map in 64-bit mode, corresponding to FXSAVE64 (whichrequires REX.W=1) and FXSAVE (REX.W=0). In the FXSAVE64 map (Table 3-51), theFPU IP and FPU DP pointers are 64-bit wide. In the FXSAVE map for 64-bit mode(Table 3-52), the FPU IP and FPU DP pointers are 32-bits.Table 3-51. Layout of the 64-bit-mode FXSAVE64 Map(requires REX.W = 1)1514131211109FPU IPMXCSR_MASK876FOPMXCSR54ReservedFTWFPU DP32FSW10FCW016ReservedST0/MM032ReservedST1/MM148ReservedST2/MM264ReservedST3/MM380ReservedST4/MM496ReservedST5/MM5112ReservedST6/MM6128ReservedST7/MM7144XMM0160XMM1176FXSAVE—Save x87 FPU, MMX Technology, and SSE StateVol.
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