Volume 2A Instruction Set Reference A-M (794101), страница 76
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2AIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.FSTENV/FNSTENV—Store x87 FPU EnvironmentINSTRUCTION SET REFERENCE, A-M#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.FSTENV/FNSTENV—Store x87 FPU EnvironmentVol.
2A 3-451INSTRUCTION SET REFERENCE, A-MFSTSW/FNSTSW—Store x87 FPU Status WordOpcodeInstruction64-BitModeCompat/Leg ModeDescription9B DD /7FSTSW m2byteValidValidStore FPU status word atm2byte after checking forpending unmasked floatingpoint exceptions.9B DF E0FSTSW AXValidValidStore FPU status word in AXregister after checking forpending unmasked floatingpoint exceptions.DD /7FNSTSW* m2byteValidValidStore FPU status word atm2byte without checking forpending unmasked floatingpoint exceptions.DF E0FNSTSW* AXValidValidStore FPU status word in AXregister without checking forpending unmasked floatingpoint exceptions.NOTES:* See IA-32 Architecture Compatibility section below.DescriptionStores the current value of the x87 FPU status word in the destination location.
Thedestination operand can be either a two-byte memory location or the AX register. TheFSTSW instruction checks for and handles pending unmasked floating-point exceptions before storing the status word; the FNSTSW instruction does not.The FNSTSW AX form of the instruction is used primarily in conditional branching (forinstance, after an FPU comparison instruction or an FPREM, FPREM1, or FXAMinstruction), where the direction of the branch depends on the state of the FPU condition code flags. (See the section titled “Branching and Conditional Moves on FPUCondition Codes” in Chapter 8 of the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 1.) This instruction can also be used to invoke exceptionhandlers (by examining the exception flags) in environments that do not use interrupts.
When the FNSTSW AX instruction is executed, the AX register is updatedbefore the processor executes any further instructions. The status stored in the AXregister is thus guaranteed to be from the completion of the prior FPU instruction.The assembler issues two instructions for the FSTSW instruction (an FWAIT instruction followed by an FNSTSW instruction), and the processor executes each of theseinstructions separately. If an exception is generated for either of these instructions,the save EIP points to the instruction that caused the exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.3-452 Vol.
2AFSTSW/FNSTSW—Store x87 FPU Status WordINSTRUCTION SET REFERENCE, A-MIA-32 Architecture CompatibilityWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it ispossible (under unusual circumstances) for an FNSTSW instruction to be interruptedprior to being executed to handle a pending FPU exception.
See the section titled“No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for adescription of these circumstances. An FNSTSW instruction cannot be interrupted inthis way on a Pentium 4, Intel Xeon, or P6 family processor.OperationDEST ← FPUStatusWord;FPU Flags AffectedThe C0, C1, C2, and C3 are undefined.Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.FSTSW/FNSTSW—Store x87 FPU Status WordVol.
2A 3-453INSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-454 Vol.
2AFSTSW/FNSTSW—Store x87 FPU Status WordINSTRUCTION SET REFERENCE, A-MFSUB/FSUBP/FISUB—SubtractOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD8 /4FSUB m32fpValidValidSubtract m32fp from ST(0)and store result in ST(0).DC /4FSUB m64fpValidValidSubtract m64fp from ST(0)and store result in ST(0).D8 E0+iFSUB ST(0), ST(i)ValidValidSubtract ST(i) from ST(0) andstore result in ST(0).DC E8+iFSUB ST(i), ST(0)ValidValidSubtract ST(0) from ST(i) andstore result in ST(i).DE E8+iFSUBP ST(i), ST(0)ValidValidSubtract ST(0) from ST(i),store result in ST(i), and popregister stack.DE E9FSUBPValidValidSubtract ST(0) from ST(1),store result in ST(1), and popregister stack.DA /4FISUB m32intValidValidSubtract m32int from ST(0)and store result in ST(0).DE /4FISUB m16intValidValidSubtract m16int from ST(0)and store result in ST(0).DescriptionSubtracts the source operand from the destination operand and stores the differencein the destination location.
The destination operand is always an FPU data register;the source operand can be a register or a memory location. Source operands inmemory can be in single-precision or double-precision floating-point format or inword or doubleword integer format.The no-operand version of the instruction subtracts the contents of the ST(0) registerfrom the ST(1) register and stores the result in ST(1). The one-operand versionsubtracts the contents of a memory location (either a floating-point or an integervalue) from the contents of the ST(0) register and stores the result in ST(0). Thetwo-operand version, subtracts the contents of the ST(0) register from the ST(i)register or vice versa.The FSUBP instructions perform the additional operation of popping the FPU registerstack following the subtraction.
To pop the register stack, the processor marks theST(0) register as empty and increments the stack pointer (TOP) by 1. The nooperand version of the floating-point subtract instructions always results in theregister stack being popped. In some assemblers, the mnemonic for this instructionis FSUB rather than FSUBP.FSUB/FSUBP/FISUB—SubtractVol. 2A 3-455INSTRUCTION SET REFERENCE, A-MThe FISUB instructions convert an integer source operand to double extended-precision floating-point format before performing the subtraction.Table 3-43 shows the results obtained when subtracting various classes of numbersfrom one another, assuming that neither overflow nor underflow occurs. Here, theSRC value is subtracted from the DEST value (DEST − SRC = result).When the difference between two operands of like sign is 0, the result is +0, exceptfor the round toward −∞ mode, in which case the result is −0.
This instruction alsoguarantees that +0 − (−0) = +0, and that −0 − (+0) = −0. When the source operand isan integer 0, it is treated as a +0.When one operand is ∞, the result is ∞ of the expected sign. If both operands are ∞ ofthe same sign, an invalid-operation exception is generated.Table 3-43. FSUB/FSUBP/FISUB ResultsSRC-•− F or − I−0+0+ F or + I+•NaN-•*-•-•-•-•-•NaN−F+•±F or ±0DESTDEST−F-•NaN−0+•−SRC±0−0− SRC-•NaN+0+•−SRC+0±0− SRC-•NaN+F+•+FDESTDEST±F or ±0-•NaN+•+•+•+•+•+•*NaNNaNNaNNaNNaNNaNNaNNaNNaNDESTNOTES:F Means finite floating-point value.I Means integer.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF Instruction = FISUBTHENDEST ← DEST − ConvertToDoubleExtendedPrecisionFP(SRC);ELSE (* Source operand is floating-point value *)DEST ← DEST − SRC;FI;3-456 Vol.
2AFSUB/FSUBP/FISUB—SubtractINSTRUCTION SET REFERENCE, A-MIF Instruction = FSUBPTHENPopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAOperand is an SNaN value or unsupported format.Operands are infinities of like sign.#DSource operand is a denormal value.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.FSUB/FSUBP/FISUB—SubtractVol.
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