Volume 2A Instruction Set Reference A-M (794101), страница 73
Текст из файла (страница 73)
2A 3-427INSTRUCTION SET REFERENCE, A-MST(7) ← SRC[ST(7)];FPU Flags AffectedThe C0, C1, C2, C3 flags are loaded.Floating-Point ExceptionsNone; however, this operation might unmask an existing exception that has beendetected but not generated, because it was masked. Here, the exception is generated at the completion of the instruction.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.3-428 Vol.
2AFRSTOR—Restore x87 FPU StateINSTRUCTION SET REFERENCE, A-M#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.FRSTOR—Restore x87 FPU StateVol.
2A 3-429INSTRUCTION SET REFERENCE, A-MFSAVE/FNSAVE—Store x87 FPU StateOpcodeInstruction64-BitModeCompat/Leg ModeDescription9B DD /6FSAVE m94/108byteValidValidStore FPU state to m94byte orm108byte after checking forpending unmasked floatingpoint exceptions. Then reinitialize the FPU.DD /6FNSAVE* m94/108byteValidValidStore FPU environment tom94byte or m108byte withoutchecking for pending unmaskedfloating-point exceptions.
Thenre-initialize the FPU.NOTES:* See IA-32 Architecture Compatibility section below.DescriptionStores the current FPU state (operating environment and register stack) at the specified destination in memory, and then re-initializes the FPU. The FSAVE instructionchecks for and handles pending unmasked floating-point exceptions before storingthe FPU state; the FNSAVE instruction does not.The FPU operating environment consists of the FPU control word, status word, tagword, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 inthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, showthe layout in memory of the stored environment, depending on the operating modeof the processor (protected or real) and the current operand-size attribute (16-bit or32-bit).
In virtual-8086 mode, the real mode layouts are used. The contents of theFPU register stack are stored in the 80 bytes immediately follow the operating environment image.The saved image reflects the state of the FPU after all floating-point instructionspreceding the FSAVE/FNSAVE instruction in the instruction stream have beenexecuted.After the FPU state has been saved, the FPU is reset to the same default values it isset to with the FINIT/FNINIT instructions (see “FINIT/FNINIT—Initialize FloatingPoint Unit” in this chapter).The FSAVE/FNSAVE instructions are typically used when the operating system needsto perform a context switch, an exception handler needs to use the FPU, or an application program needs to pass a “clean” FPU to a procedure.The assembler issues two instructions for the FSAVE instruction (an FWAIT instruction followed by an FNSAVE instruction), and the processor executes each of these3-430 Vol.
2AFSAVE/FNSAVE—Store x87 FPU StateINSTRUCTION SET REFERENCE, A-Minstructions separately. If an exception is generated for either of these instructions,the save EIP points to the instruction that caused the exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityFor Intel math coprocessors and FPUs prior to the Intel Pentium processor, an FWAITinstruction should be executed before attempting to read from the memory imagestored with a prior FSAVE/FNSAVE instruction.
This FWAIT instruction helps ensurethat the storage operation has been completed.When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it ispossible (under unusual circumstances) for an FNSAVE instruction to be interruptedprior to being executed to handle a pending FPU exception. See the section titled“No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for adescription of these circumstances. An FNSAVE instruction cannot be interrupted inthis way on a Pentium 4, Intel Xeon, or P6 family processor.Operation(* Save FPU State and Registers *)DEST[FPUControlWord] ← FPUControlWord;DEST[FPUStatusWord] ← FPUStatusWord;DEST[FPUTagWord] ← FPUTagWord;DEST[FPUDataPointer] ← FPUDataPointer;DEST[FPUInstructionPointer] ← FPUInstructionPointer;DEST[FPULastInstructionOpcode] ← FPULastInstructionOpcode;DEST[ST(0)] ← ST(0);DEST[ST(1)] ← ST(1);DEST[ST(2)] ← ST(2);DEST[ST(3)] ← ST(3);DEST[ST(4)]← ST(4);DEST[ST(5)] ← ST(5);DEST[ST(6)] ← ST(6);DEST[ST(7)] ← ST(7);(* Initialize FPU *)FPUControlWord ← 037FH;FPUStatusWord ← 0;FPUTagWord ← FFFFH;FPUDataPointer ← 0;FPUInstructionPointer ← 0;FPULastInstructionOpcode ← 0;FSAVE/FNSAVE—Store x87 FPU StateVol.
2A 3-431INSTRUCTION SET REFERENCE, A-MFPU Flags AffectedThe C0, C1, C2, and C3 flags are saved and then cleared.Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)If destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.3-432 Vol.
2AFSAVE/FNSAVE—Store x87 FPU StateINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.FSAVE/FNSAVE—Store x87 FPU StateVol. 2A 3-433INSTRUCTION SET REFERENCE, A-MFSCALE—ScaleOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 FDFSCALEValidValidScale ST(0) by ST(1).DescriptionTruncates the value in the source operand (toward 0) to an integral value and addsthat value to the exponent of the destination operand.
The destination and sourceoperands are floating-point values located in registers ST(0) and ST(1), respectively.This instruction provides rapid multiplication or division by integral powers of 2. Thefollowing table shows the results obtained when scaling various classes of numbers,assuming that neither overflow nor underflow occurs.Table 3-39. FSCALE ResultsST(1)ST(0)-•−F−0+0+F+•NaN-•NaN-•-•-•-•-•NaN−F−0−F−F−F−F-•NaN−0-0-0-0-0-0NaNNaN+0+0+0+0+0+0NaNNaN+F+0+F+F+F+F+•NaN+•NaN+•+•+•+•+•NaNNaNNaNNaNNaNNaNNaNNaNNaNNOTES:F Means finite floating-point value.In most cases, only the exponent is changed and the mantissa (significand) remainsunchanged.
However, when the value being scaled in ST(0) is a denormal value, themantissa is also changed and the result may turn out to be a normalized number.Similarly, if overflow or underflow results from a scale operation, the resultingmantissa will differ from the source’s mantissa.The FSCALE instruction can also be used to reverse the action of the FXTRACTinstruction, as shown in the following example:FXTRACT;FSCALE;FSTP ST(1);In this example, the FXTRACT instruction extracts the significand and exponent fromthe value in ST(0) and stores them in ST(0) and ST(1) respectively. The FSCALE thenscales the significand in ST(0) by the exponent in ST(1), recreating the original value3-434 Vol.
2AFSCALE—ScaleINSTRUCTION SET REFERENCE, A-Mbefore the FXTRACT operation was performed. The FSTP ST(1) instruction overwritesthe exponent (extracted by the FXTRACT instruction) with the recreated value, whichreturns the stack to its original state with only one register [ST(0)] occupied.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationST(0) ← ST(0) ∗ 2RoundTowardZero(ST(1));FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IASource operand is an SNaN value or unsupported format.#DSource operand is a denormal value.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FSCALE—ScaleVol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
