Volume 2A Instruction Set Reference A-M (794101), страница 69
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2AFISTTP—Store Integer with TruncationINSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.If the LOCK prefix is used.FISTTP—Store Integer with TruncationVol. 2A 3-397INSTRUCTION SET REFERENCE, A-MFLD—Load Floating Point ValueOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 /0FLD m32fpValidValidPush m32fp onto the FPU register stack.DD /0FLD m64fpValidValidPush m64fp onto the FPU register stack.DB /5FLD m80fpValidValidPush m80fp onto the FPU register stack.D9 C0+iFLD ST(i)ValidValidPush ST(i) onto the FPU register stack.DescriptionPushes the source operand onto the FPU register stack.
The source operand can be insingle-precision, double-precision, or double extended-precision floating-pointformat. If the source operand is in single-precision or double-precision floating-pointformat, it is automatically converted to the double extended-precision floating-pointformat before being pushed on the stack.The FLD instruction can also push the value in a selected FPU register [ST(i)] onto thestack. Here, pushing register ST(0) duplicates the stack top.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF SRC is ST(i)THENtemp ← ST(i);FI;TOP ← TOP − 1;IF SRC is memory-operandTHENST(0) ← ConvertToDoubleExtendedPrecisionFP(SRC);ELSE (* SRC is ST(i) *)ST(0) ← temp;FI;FPU Flags AffectedC1Set to 1 if stack overflow occurred; otherwise, set to 0.C0, C2, C3Undefined.Floating-Point Exceptions#IS3-398 Vol.
2AStack underflow or overflow occurred.FLD—Load Floating Point ValueINSTRUCTION SET REFERENCE, A-M#IASource operand is an SNaN. Does not occur if the sourceoperand is in double extended-precision floating-point format(FLD m80fp or FLD ST(i)).#DSource operand is a denormal value. Does not occur if thesource operand is in double extended-precision floating-pointformat.Protected Mode Exceptions#GP(0)If destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.FLD—Load Floating Point ValueVol.
2A 3-399INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-400 Vol. 2AFLD—Load Floating Point ValueINSTRUCTION SET REFERENCE, A-MFLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load ConstantOpcode*Instruction64-BitModeCompat/Leg ModeDescriptionD9 E8FLD1ValidValidPush +1.0 onto the FPU register stack.D9 E9FLDL2TValidValidPush log210 onto the FPU register stack.D9 EAFLDL2EValidValidPush log2e onto the FPU register stack.D9 EBFLDPIValidValidPush π onto the FPU register stack.D9 ECFLDLG2ValidValidPush log102 onto the FPU register stack.D9 EDFLDLN2ValidValidPush loge2 onto the FPU register stack.D9 EEFLDZValidValidPush +0.0 onto the FPU register stack.NOTES:* See IA-32 Architecture Compatibility section below.DescriptionPush one of seven commonly used constants (in double extended-precision floatingpoint format) onto the FPU register stack.
The constants that can be loaded withthese instructions include +1.0, +0.0, log210, log2e, π, log102, and loge2. For eachconstant, an internal 66-bit constant is rounded (as specified by the RC field in theFPU control word) to double extended-precision floating-point format.
The inexactresult exception (#P) is not generated as a result of the rounding, nor is the C1 flagset in the x87 FPU status word if the value is rounded up.See the section titled “Pi” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of the π constant.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityWhen the RC field is set to round-to-nearest, the FPU produces the same constantsthat is produced by the Intel 8087 and Intel 287 math coprocessors.OperationTOP ← TOP − 1;ST(0) ← CONSTANT;FPU Flags AffectedC1Set to 1 if stack overflow occurred; otherwise, set to 0.C0, C2, C3Undefined.FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load ConstantVol.
2A 3-401INSTRUCTION SET REFERENCE, A-MFloating-Point Exceptions#ISStack overflow occurred.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-402 Vol.
2AFLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load ConstantINSTRUCTION SET REFERENCE, A-MFLDCW—Load x87 FPU Control WordOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 /5FLDCW m2byteValidValidLoad FPU control word from m2byte.DescriptionLoads the 16-bit source operand into the FPU control word. The source operand is amemory location.
This instruction is typically used to establish or change the FPU’smode of operation.If one or more exception flags are set in the FPU status word prior to loading a newFPU control word and the new control word unmasks one or more of those exceptions, a floating-point exception will be generated upon execution of the nextfloating-point instruction (except for the no-wait floating-point instructions, see thesection titled “Software Exception Handling” in Chapter 8 of the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 1). To avoid raising exceptionswhen changing FPU operating modes, clear any pending exceptions (using the FCLEXor FNCLEX instruction) before loading the new control word.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationFPUControlWord ← SRC;FPU Flags AffectedC0, C1, C2, C3 undefined.Floating-Point ExceptionsNone; however, this operation might unmask a pending exception in the FPU statusword.
That exception is then generated upon execution of the next “waiting” floatingpoint instruction.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.FLDCW—Load x87 FPU Control WordVol.
2A 3-403INSTRUCTION SET REFERENCE, A-M#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-404 Vol.
2AFLDCW—Load x87 FPU Control WordINSTRUCTION SET REFERENCE, A-MFLDENV—Load x87 FPU EnvironmentOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 /4FLDENV m14/28byteValidValidLoad FPU environment fromm14byte or m28byte.DescriptionLoads the complete x87 FPU operating environment from memory into the FPU registers. The source operand specifies the first byte of the operating-environment data inmemory. This data is typically written to the specified memory location by a FSTENVor FNSTENV instruction.The FPU operating environment consists of the FPU control word, status word, tagword, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 inthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, showthe layout in memory of the loaded environment, depending on the operating modeof the processor (protected or real) and the current operand-size attribute (16-bit or32-bit).
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