Volume 2A Instruction Set Reference A-M (794101), страница 64
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If the invalid-operation exception is not masked, an invalidarithmetic-operand exception (#IA) is generated and no value is stored in the desti-FBSTP—Store BCD Integer and PopVol. 2A 3-353INSTRUCTION SET REFERENCE, A-Mnation operand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationDEST ← BCD(ST(0));PopRegisterStack;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAConverted value that exceeds 18 BCD digits in length.Source operand is an SNaN, QNaN, ±∞, or in an unsupportedformat.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#GP(0)If a segment register is being loaded with a segment selectorthat points to a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.3-354 Vol.
2AFBSTP—Store BCD Integer and PopINSTRUCTION SET REFERENCE, A-M#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.FBSTP—Store BCD Integer and PopVol.
2A 3-355INSTRUCTION SET REFERENCE, A-MFCHS—Change SignOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 E0FCHSValidValidComplements sign of ST(0).DescriptionComplements the sign bit of ST(0). This operation changes a positive value into anegative value of equal magnitude or vice versa. The following table shows theresults obtained when changing the sign of various classes of numbers.Table 3-25. FCHS ResultsST(0) SRCST(0) DEST−•+•−F+F−0+0+0−0+F−F+•−•NaNNaNNOTES:* F means finite floating-point value.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationSignBit(ST(0)) ← NOT (SignBit(ST(0)));FPU Flags AffectedC1Set to 0 if stack underflow occurred; otherwise, set to 0.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.3-356 Vol.
2AFCHS—Change SignINSTRUCTION SET REFERENCE, A-MReal-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FCHS—Change SignVol. 2A 3-357INSTRUCTION SET REFERENCE, A-MFCLEX/FNCLEX—Clear ExceptionsOpcode*Instruction64-BitModeCompat/Leg ModeDescription9B DB E2FCLEXValidValidClear floating-point exception flags afterchecking for pending unmasked floatingpoint exceptions.DB E2FNCLEX*ValidValidClear floating-point exception flagswithout checking for pending unmaskedfloating-point exceptions.NOTES:* See IA-32 Architecture Compatibility section below.DescriptionClears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the exceptionsummary status flag (ES), the stack fault flag (SF), and the busy flag (B) in the FPUstatus word.
The FCLEX instruction checks for and handles any pending unmaskedfloating-point exceptions before clearing the exception flags; the FNCLEX instructiondoes not.The assembler issues two instructions for the FCLEX instruction (an FWAIT instruction followed by an FNCLEX instruction), and the processor executes each of theseinstructions separately. If an exception is generated for either of these instructions,the save EIP points to the instruction that caused the exception.IA-32 Architecture CompatibilityWhen operating a Pentium or Intel486 processor in MS-DOS* compatibility mode, itis possible (under unusual circumstances) for an FNCLEX instruction to be interrupted prior to being executed to handle a pending FPU exception.
See the sectiontitled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D ofthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for adescription of these circumstances. An FNCLEX instruction cannot be interrupted inthis way on a Pentium 4, Intel Xeon, or P6 family processor.This instruction affects only the x87 FPU floating-point exception flags. It does notaffect the SIMD floating-point exception flags in the MXCRS register.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationFPUStatusWord[0:7] ← 0;FPUStatusWord[15] ← 0;3-358 Vol. 2AFCLEX/FNCLEX—Clear ExceptionsINSTRUCTION SET REFERENCE, A-MFPU Flags AffectedThe PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared.The C0, C1, C2, and C3 flags are undefined.Floating-Point ExceptionsNone.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FCLEX/FNCLEX—Clear ExceptionsVol.
2A 3-359INSTRUCTION SET REFERENCE, A-MFCMOVcc—Floating-Point Conditional MoveOpcode*Instruction64-BitModeCompat/Leg Mode*DescriptionDA C0+iFCMOVB ST(0), ST(i)ValidValidMove if below (CF=1).DA C8+iFCMOVE ST(0), ST(i)ValidValidMove if equal (ZF=1).DA D0+iFCMOVBE ST(0), ST(i)ValidValidMove if below or equal (CF=1 orZF=1).DA D8+iFCMOVU ST(0), ST(i)ValidValidMove if unordered (PF=1).DB C0+iFCMOVNB ST(0), ST(i)ValidValidMove if not below (CF=0).DB C8+iFCMOVNE ST(0), ST(i)ValidValidMove if not equal (ZF=0).DB D0+iFCMOVNBE ST(0), ST(i)ValidValidMove if not below or equal (CF=0and ZF=0).DB D8+iFCMOVNU ST(0), ST(i)ValidValidMove if not unordered (PF=0).NOTES:* See IA-32 Architecture Compatibility section below.DescriptionTests the status flags in the EFLAGS register and moves the source operand (secondoperand) to the destination operand (first operand) if the given test condition is true.The condition for each mnemonic os given in the Description column above and inChapter 8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 1.
The source operand is always in the ST(i) register and the destinationoperand is always ST(0).The FCMOVcc instructions are useful for optimizing small IF constructions. They alsohelp eliminate branching overhead for IF operations and the possibility of branchmispredictions by the processor.A processor may not support the FCMOVcc instructions. Software can check if theFCMOVcc instructions are supported by checking the processor’s feature informationwith the CPUID instruction (see “COMISS—Compare Scalar Ordered Single-PrecisionFloating-Point Values and Set EFLAGS” in this chapter).
If both the CMOV and FPUfeature bits are set, the FCMOVcc instructions are supported.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityThe FCMOVcc instructions were introduced to the IA-32 Architecture in the P6 familyprocessors and are not available in earlier IA-32 processors.3-360 Vol. 2AFCMOVcc—Floating-Point Conditional MoveINSTRUCTION SET REFERENCE, A-MOperationIF condition TRUETHEN ST(0) ← ST(i);FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.Integer Flags AffectedNone.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FCMOVcc—Floating-Point Conditional MoveVol.
2A 3-361INSTRUCTION SET REFERENCE, A-MFCOM/FCOMP/FCOMPP—Compare Floating Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD8 /2FCOM m32fpValidValidCompare ST(0) with m32fp.DC /2FCOM m64fpValidValidCompare ST(0) with m64fp.D8 D0+iFCOM ST(i)ValidValidCompare ST(0) with ST(i).D8 D1FCOMValidValidCompare ST(0) with ST(1).D8 /3FCOMP m32fpValidValidCompare ST(0) with m32fp andpop register stack.DC /3FCOMP m64fpValidValidCompare ST(0) with m64fp andpop register stack.D8 D8+iFCOMP ST(i)ValidValidCompare ST(0) with ST(i) and popregister stack.D8 D9FCOMPValidValidCompare ST(0) with ST(1) and popregister stack.DE D9FCOMPPValidValidCompare ST(0) with ST(1) and popregister stack twice.DescriptionCompares the contents of register ST(0) and source value and sets condition codeflags C0, C2, and C3 in the FPU status word according to the results (see the tablebelow).
The source operand can be a data register or a memory location. If no sourceoperand is given, the value in ST(0) is compared with the value in ST(1). The sign ofzero is ignored, so that –0.0 is equal to +0.0.Table 3-26. FCOM/FCOMP/FCOMPP ResultsConditionC3C2C0ST(0) > SRC000ST(0) < SRC001ST(0) = SRC100Unordered*111NOTES:* Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.This instruction checks the class of the numbers being compared (see“FXAM—Examine ModR/M” in this chapter). If either operand is a NaN or is in anunsupported format, an invalid-arithmetic-operand exception (#IA) is raised and, ifthe exception is masked, the condition flags are set to “unordered.” If the invalidarithmetic-operand exception is unmasked, the condition code flags are not set.3-362 Vol. 2AFCMOVcc—Floating-Point Conditional MoveINSTRUCTION SET REFERENCE, A-MThe FCOMP instruction pops the register stack following the comparison operationand the FCOMPP instruction pops the register stack twice following the comparisonoperation.
To pop the register stack, the processor marks the ST(0) register asempty and increments the stack pointer (TOP) by 1.The FCOM instructions perform the same operation as the FUCOM instructions. Theonly difference is how they handle QNaN operands. The FCOM instructions raise aninvalid-arithmetic-operand exception (#IA) when either or both of the operands is aNaN value or is in an unsupported format. The FUCOM instructions perform the sameoperation as the FCOM instructions, except that they do not generate an invalidarithmetic-operand exception for QNaNs.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationCASE (relation of operands) OFST > SRC:C3, C2, C0 ← 000;ST < SRC:C3, C2, C0 ← 001;ST = SRC:C3, C2, C0 ← 100;ESAC;IF ST(0) or SRC = NaN or unsupported formatTHEN#IAIF FPUControlWord.IM = 1THENC3, C2, C0 ← 111;FI;FI;IF Instruction = FCOMPTHENPopRegisterStack;FI;IF Instruction = FCOMPPTHENPopRegisterStack;PopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred; otherwise, set to 0.C0, C2, C3See table on previous page.FCMOVcc—Floating-Point Conditional MoveVol.
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