Volume 2A Instruction Set Reference A-M (794101), страница 68
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The data registers in the register stack are left unchanged, butthey are all tagged as empty (11B). Both the instruction and data pointers arecleared.The FINIT instruction checks for and handles any pending unmasked floating-pointexceptions before performing the initialization; the FNINIT instruction does not.The assembler issues two instructions for the FINIT instruction (an FWAIT instructionfollowed by an FNINIT instruction), and the processor executes each of these instructions in separately.
If an exception is generated for either of these instructions, thesave EIP points to the instruction that caused the exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it ispossible (under unusual circumstances) for an FNINIT instruction to be interruptedprior to being executed to handle a pending FPU exception. See the section titled“No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for adescription of these circumstances.
An FNINIT instruction cannot be interrupted inthis way on a Pentium 4, Intel Xeon, or P6 family processor.In the Intel387 math coprocessor, the FINIT/FNINIT instruction does not clear theinstruction and data pointers.This instruction affects only the x87 FPU. It does not affect the XMM and MXCSRregisters.FINIT/FNINIT—Initialize Floating-Point UnitVol. 2A 3-389INSTRUCTION SET REFERENCE, A-MOperationFPUControlWord ← 037FH;FPUStatusWord ← 0;FPUTagWord ← FFFFH;FPUDataPointer ← 0;FPUInstructionPointer ← 0;FPULastInstructionOpcode ← 0;FPU Flags AffectedC0, C1, C2, C3 set to 0.Floating-Point ExceptionsNone.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-390 Vol.
2AFINIT/FNINIT—Initialize Floating-Point UnitINSTRUCTION SET REFERENCE, A-MFIST/FISTP—Store IntegerOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionDF /2FIST m16intValidValidStore ST(0) in m16int.DB /2FIST m32intValidValidStore ST(0) in m32int.DF /3FISTP m16intValidValidStore ST(0) in m16int and popregister stack.DB /3FISTP m32intValidValidStore ST(0) in m32int and popregister stack.DF /7FISTP m64intValidValidStore ST(0) in m64int and popregister stack.DescriptionThe FIST instruction converts the value in the ST(0) register to a signed integer andstores the result in the destination operand.
Values can be stored in word or doubleword integer format. The destination operand specifies the address where the firstbyte of the destination value is to be stored.The FISTP instruction performs the same operation as the FIST instruction and thenpops the register stack. To pop the register stack, the processor marks the ST(0)register as empty and increments the stack pointer (TOP) by 1.
The FISTP instructionalso stores values in quadword integer format.The following table shows the results obtained when storing various classes ofnumbers in integer format.Table 3-32. FIST/FISTP ResultsST(0)DEST−• or Value Too Large for DEST Format*F ≤ −1−I−1 < F < −0**−00+00+0<F<+1**F≥+1+I+• or Value Too Large for DEST Format*FIST/FISTP—Store IntegerVol.
2A 3-391INSTRUCTION SET REFERENCE, A-MTable 3-32. FIST/FISTP Results (Contd.)ST(0)DESTNaN*NOTES:F Means finite floating-point value.I Means integer.* Indicates floating-point invalid-operation (#IA) exception.** 0 or ±1, depending on the rounding mode.If the source value is a non-integral value, it is rounded to an integer value, accordingto the rounding mode specified by the RC field of the FPU control word.If the converted value is too large for the destination format, or if the source operandis an ∞, SNaN, QNAN, or is in an unsupported format, an invalid-arithmetic-operandcondition is signaled.
If the invalid-operation exception is not masked, an invalidarithmetic-operand exception (#IA) is generated and no value is stored in the destination operand. If the invalid-operation exception is masked, the integer indefinitevalue is stored in memory.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationDEST ← Integer(ST(0));IF Instruction = FISTPTHENPopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Indicates rounding direction of if the inexact exception (#P) isgenerated: 0 ← not roundup; 1 ← roundup.Set to 0 otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAConverted value is too large for the destination format.#PValue cannot be represented exactly in destination format.Source operand is an SNaN, QNaN, ±∞, or unsupported format.3-392 Vol.
2AFIST/FISTP—Store IntegerINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.FIST/FISTP—Store IntegerVol.
2A 3-393INSTRUCTION SET REFERENCE, A-M#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-394 Vol. 2AFIST/FISTP—Store IntegerINSTRUCTION SET REFERENCE, A-MFISTTP—Store Integer with TruncationOpcodeInstruction64-Bit Mode Compat/Leg ModeDescriptionDF /1FISTTP m16intValidValidStore ST(0) in m16int withtruncation.DB /1FISTTP m32intValidValidStore ST(0) in m32int withtruncation.DD /1FISTTP m64intValidValidStore ST(0) in m64int withtruncation.DescriptionFISTTP converts the value in ST into a signed integer using truncation (chop) asrounding mode, transfers the result to the destination, and pop ST.
FISTTP acceptsword, short integer, and long integer destinations.The following table shows the results obtained when storing various classes ofnumbers in integer format.Table 3-33. FISTTP ResultsST(0)−• or Value Too Large for DEST FormatF≤ −1DEST*−I−1<F<+10FŠ+1+I+• or Value Too Large for DEST Format*NaN*NOTES:F Means finite floating-point value.Ι Means integer.∗ Indicates floating-point invalid-operation (#IA) exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationDEST ← ST;pop ST;Flags AffectedC1 is cleared; C0, C2, C3 undefined.FISTTP—Store Integer with TruncationVol.
2A 3-395INSTRUCTION SET REFERENCE, A-MNumeric ExceptionsInvalid, Stack Invalid (stack underflow), Precision.Protected Mode Exceptions#GP(0)If the destination is in a nonwritable segment.For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#NMIf CR0.EM[bit 2] = 1.If CR0.TS[bit 3] = 1.#UDIf CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Real Address Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.#NMIf CR0.EM[bit 2] = 1.#UDIf CPUID.01H:ECX.SSE3[bit 0] = 0.If CR0.TS[bit 3] = 1.If the LOCK prefix is used.Virtual 8086 Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.#NMIf CR0.EM[bit 2] = 1.#UDIf CPUID.01H:ECX.SSE3[bit 0] = 0.If CR0.TS[bit 3] = 1.If the LOCK prefix is used.#PF(fault-code)For a page fault.#AC(0)For unaligned memory reference if the current privilege is 3.Compatibility Mode ExceptionsSame exceptions as in protected mode.3-396 Vol.
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