Volume 2A Instruction Set Reference A-M (794101), страница 65
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2A 3-363INSTRUCTION SET REFERENCE, A-MFloating-Point Exceptions#ISStack underflow occurred.#IAOne or both operands are NaN values or have unsupportedformats.#DOne or both operands are denormal values.Register is marked empty.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.3-364 Vol.
2AFCMOVcc—Floating-Point Conditional MoveINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.FCMOVcc—Floating-Point Conditional MoveVol.
2A 3-365INSTRUCTION SET REFERENCE, A-MFCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values andSet EFLAGSOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionDB F0+iFCOMI ST, ST(i)ValidValidCompare ST(0) with ST(i) and set statusflags accordingly.DF F0+iFCOMIP ST, ST(i)ValidValidCompare ST(0) with ST(i), set status flagsaccordingly, and pop register stack.DB E8+iFUCOMI ST, ST(i)ValidValidCompare ST(0) with ST(i), check forordered values, and set status flagsaccordingly.DF E8+iFUCOMIP ST, ST(i) ValidValidCompare ST(0) with ST(i), check forordered values, set status flagsaccordingly, and pop register stack.DescriptionPerforms an unordered comparison of the contents of registers ST(0) and ST(i) andsets the status flags ZF, PF, and CF in the EFLAGS register according to the results(see the table below). The sign of zero is ignored for comparisons, so that –0.0 isequal to +0.0.Table 3-27.
FCOMI/FCOMIP/ FUCOMI/FUCOMIP ResultsComparison Results*ZFPFCFST0 > ST(i)000ST0 < ST(i)001ST0 = ST(i)100Unordered**111NOTES:* See the IA-32 Architecture Compatibility section below.** Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.An unordered comparison checks the class of the numbers being compared (see“FXAM—Examine ModR/M” in this chapter). The FUCOMI/FUCOMIP instructionsperform the same operations as the FCOMI/FCOMIP instructions.
The only differenceis that the FUCOMI/FUCOMIP instructions raise the invalid-arithmetic-operandexception (#IA) only when either or both operands are an SNaN or are in an unsupported format; QNaNs cause the condition code flags to be set to unordered, but donot cause an exception to be generated. The FCOMI/FCOMIP instructions raise aninvalid-operation exception when either or both of the operands are a NaN value ofany kind or are in an unsupported format.3-366 Vol. 2AFCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-MIf the operation results in an invalid-arithmetic-operand exception being raised, thestatus flags in the EFLAGS register are set only if the exception is masked.The FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions clear the OF flag in theEFLAGS register (regardless of whether an invalid-operation exception is detected).The FCOMIP and FUCOMIP instructions also pop the register stack following thecomparison operation.
To pop the register stack, the processor marks the ST(0)register as empty and increments the stack pointer (TOP) by 1.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityThe FCOMI/FCOMIP/FUCOMI/FUCOMIP instructions were introduced to the IA-32Architecture in the P6 family processors and are not available in earlier IA-32 processors.OperationCASE (relation of operands) OFST(0) > ST(i):ZF, PF, CF ← 000;ST(0) < ST(i):ZF, PF, CF ← 001;ST(0) = ST(i):ZF, PF, CF ← 100;ESAC;IF Instruction is FCOMI or FCOMIPTHENIF ST(0) or ST(i) = NaN or unsupported formatTHEN#IAIF FPUControlWord.IM = 1THENZF, PF, CF ← 111;FI;FI;FI;IF Instruction is FUCOMI or FUCOMIPTHENIF ST(0) or ST(i) = QNaN, but not SNaN or unsupported formatTHENZF, PF, CF ← 111;ELSE (* ST(0) or ST(i) is SNaN or unsupported format *)#IA;IF FPUControlWord.IM = 1THENFCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGSVol.
2A 3-367INSTRUCTION SET REFERENCE, A-MZF, PF, CF ← 111;FI;FI;FI;IF Instruction is FCOMIP or FUCOMIPTHENPopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred; otherwise, set to 0.C0, C2, C3Not affected.Floating-Point Exceptions#ISStack underflow occurred.#IA(FCOMI or FCOMIP instruction) One or both operands are NaNvalues or have unsupported formats.(FUCOMI or FUCOMIP instruction) One or both operands areSNaN values (but not QNaNs) or have undefined formats.Detection of a QNaN value does not raise an invalid-operandexception.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-368 Vol.
2AFCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-MFCOS—CosineOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 FFFCOSValidValidReplace ST(0) with its cosine.DescriptionComputes the cosine of the source operand in register ST(0) and stores the result inST(0). The source operand must be given in radians and must be within the range −263 to +263. The following table shows the results obtained when taking the cosine ofvarious classes of numbers.Table 3-28. FCOS ResultsST(0) SRCST(0) DEST−•*−F−1 to +1−0+1+0+1+F− 1 to + 1+•*NaNNaNNOTES:F Means finite floating-point value.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.If the source operand is outside the acceptable range, the C2 flag in the FPU statusword is set, and the value in register ST(0) remains unchanged.
The instruction doesnot raise an exception when the source operand is out of range. It is up to theprogram to check the C2 flag for out-of-range conditions. Source values outside therange −263 to +263 can be reduced to the range of the instruction by subtracting anappropriate integer multiple of 2π or by using the FPREM instruction with a divisor of2π. See the section titled “Pi” in Chapter 8 of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1, for a discussion of the proper value to usefor π in performing such reductions.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF |ST(0)| < 263THENC2 ← 0;FCOS—CosineVol.
2A 3-369INSTRUCTION SET REFERENCE, A-MST(0) ← cosine(ST(0));ELSE (* Source operand is out-of-range *)C2 ← 1;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.Undefined if C2 is 1.C2Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0.C0, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IASource operand is an SNaN value, ∞, or unsupported format.#DSource is a denormal value.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-370 Vol.
2AFCOS—CosineINSTRUCTION SET REFERENCE, A-MFDECSTP—Decrement Stack-Top PointerOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 F6FDECSTPValidValidDecrement TOP field in FPU statusword.DescriptionSubtracts one from the TOP field of the FPU status word (decrements the top-ofstack pointer). If the TOP field contains a 0, it is set to 7. The effect of this instructionis to rotate the stack by one position.
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