Volume 2A Instruction Set Reference A-M (794101), страница 62
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2AEMMS—Empty MMX Technology StateINSTRUCTION SET REFERENCE, A-M#MFIf there is a pending FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.EMMS—Empty MMX Technology StateVol.
2A 3-335INSTRUCTION SET REFERENCE, A-MENTER—Make Stack Frame for Procedure ParametersOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeC8 iw 00ENTER imm16, 0AValidValidCreate a stack frame for aprocedure.C8 iw 01ENTER imm16,1AValidValidCreate a nested stack framefor a procedure.C8 iw ibENTER imm16,imm8AValidValidCreate a nested stack framefor a procedure.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4Aiwimm8NANADescriptionCreates a stack frame for a procedure. The first operand (size operand) specifies thesize of the stack frame (that is, the number of bytes of dynamic storage allocated onthe stack for the procedure). The second operand (nesting level operand) gives thelexical nesting level (0 to 31) of the procedure. The nesting level determines thenumber of stack frame pointers that are copied into the “display area” of the newstack frame from the preceding frame. Both of these operands are immediate values.The stack-size attribute determines whether the BP (16 bits), EBP (32 bits), or RBP(64 bits) register specifies the current frame pointer and whether SP (16 bits), ESP(32 bits), or RSP (64 bits) specifies the stack pointer.
In 64-bit mode, stack-sizeattribute is always 64-bits.The ENTER and companion LEAVE instructions are provided to support block structured languages. The ENTER instruction (when used) is typically the first instructionin a procedure and is used to set up a new stack frame for a procedure. The LEAVEinstruction is then used at the end of the procedure (just before the RET instruction)to release the stack frame.If the nesting level is 0, the processor pushes the frame pointer from the BP/EBP/RBPregister onto the stack, copies the current stack pointer from the SP/ESP/RSPregister into the BP/EBP/RBP register, and loads the SP/ESP/RSP register with thecurrent stack-pointer value minus the value in the size operand.
For nesting levels of1 or greater, the processor pushes additional frame pointers on the stack beforeadjusting the stack pointer. These additional frame pointers provide the called procedure with access points to other nested frames on the stack. See “Procedure Calls forBlock-Structured Languages” in Chapter 6 of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1, for more information about the actions ofthe ENTER instruction.3-336 Vol. 2AENTER—Make Stack Frame for Procedure ParametersINSTRUCTION SET REFERENCE, A-MThe ENTER instruction causes a page fault whenever a write using the final value ofthe stack pointer (within the current stack segment) would do so.In 64-bit mode, default operation size is 64 bits; 32-bit operation size cannot beencoded.OperationNestingLevel ← NestingLevel MOD 32IF 64-Bit Mode (StackSize = 64)THENPush(RBP);FrameTemp ← RSP;ELSE IF StackSize = 32THENPush(EBP);FrameTemp ← ESP; FI;ELSE (* StackSize = 16 *)Push(BP);FrameTemp ← SP;FI;IF NestingLevel = 0THEN GOTO CONTINUE;FI;IF (NestingLevel > 1)THEN FOR i ← 1 to (NestingLevel - 1)DOIF 64-Bit Mode (StackSize = 64)THENRBP ← RBP - 8;Push([RBP]); (* Quadword push *)ELSE IF OperandSize = 32THENIF StackSize = 32EBP ← EBP - 4;Push([EBP]); (* Doubleword push *)ELSE (* StackSize = 16 *)BP ← BP - 4;Push([BP]); (* Doubleword push *)FI;FI;ELSE (* OperandSize = 16 *)IF StackSize = 32THENENTER—Make Stack Frame for Procedure ParametersVol.
2A 3-337INSTRUCTION SET REFERENCE, A-MEBP ← EBP - 2;Push([EBP]); (* Word push *)ELSE (* StackSize = 16 *)BP ← BP - 2;Push([BP]); (* Word push *)FI;FI;OD;FI;IF 64-Bit Mode (StackSize = 64)THENPush(FrameTemp); (* Quadword push *)ELSE IF OperandSize = 32THENPush(FrameTemp); FI; (* Doubleword push *)ELSE (* OperandSize = 16 *)Push(FrameTemp); (* Word push *)FI;CONTINUE:IF 64-Bit Mode (StackSize = 64)THENRBP ← FrameTemp;RSP ← RSP − Size;ELSE IF StackSize = 32THENEBP ← FrameTemp;ESP ← ESP − Size; FI;ELSE (* StackSize = 16 *)BP ← FrameTemp;SP ← SP − Size;FI;END;Flags AffectedNone.Protected Mode Exceptions#SS(0)3-338 Vol.
2AIf the new value of the SP or ESP register is outside the stacksegment limit.ENTER—Make Stack Frame for Procedure ParametersINSTRUCTION SET REFERENCE, A-M#PF(fault-code)If a page fault occurs or if a write using the final value of thestack pointer (within the current stack segment) would cause apage fault.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#SSIf the new value of the SP or ESP register is outside the stacksegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#SS(0)If the new value of the SP or ESP register is outside the stacksegment limit.#PF(fault-code)If a page fault occurs or if a write using the final value of thestack pointer (within the current stack segment) would cause apage fault.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If the stack address is in a non-canonical form.#PF(fault-code)If a page fault occurs or if a write using the final value of thestack pointer (within the current stack segment) would cause apage fault.#UDIf the LOCK prefix is used.ENTER—Make Stack Frame for Procedure ParametersVol.
2A 3-339INSTRUCTION SET REFERENCE, A-MEXTRACTPS — Extract Packed Single Precision Floating-Point ValueOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F 3A 17EXTRACTPSreg/m32, xmm2,imm8AValidValid/r ibExtract a single-precisionfloating-point value fromxmm2 at the source offsetspecified by imm8 and storethe result to reg or m32.The upper 32 bits of r64 iszeroed if reg is r64.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (w)ModRM:reg (r)imm8NADescriptionExtract a single-precision floating-point value from the source xmm register (secondargument) at an offset determined by imm8[1-0]*32.
The extracted single precisionfloating-point value is stored into the low 32-bits of the destination register or to the32-bit memory location.When in 64-bit mode and the destination operand is a general purpose register(GPR), the default operand size is 64 bits. The upper 32 bits of the 64-bit register isfilled with zero.OperationIF (64-Bit Mode and the destination is a GPR )THENDEST[31:0] Å (SRC >> (32 * imm8[1:0])) AND 0FFFFFFFFh;DEST[63:32] Å ZERO_FILL;ELSEDEST[31:0] Å (SRC >> (32 * imm8[1:0])) AND 0FFFFFFFFh;FI;Intel C/C++ Compiler Intrinsic EquivalentEXTRACTPSint _mm_extract_ps(__m128 src, const int ndx);SIMD Floating-Point ExceptionsNone3-340 Vol.
2AEXTRACTPS — Extract Packed Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS, or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real Mode Exceptions#GPif any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.Virtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in Protected Mode.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#PF(fault-code)For a page fault.#NMIf TS in CR0 is set.#UDIf EM in CR0 is set.If OSFXSR in CR4 is 0.EXTRACTPS — Extract Packed Single Precision Floating-Point ValueVol.
2A 3-341INSTRUCTION SET REFERENCE, A-MIf CPUID feature flag ECX.SSE4_1 is 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.#AC(0)3-342 Vol. 2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.EXTRACTPS — Extract Packed Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-MF2XM1—Compute 2x–1OpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 F0F2XM1ValidValidReplace ST(0) with (2ST(0) – 1).DescriptionComputes the exponential value of 2 to the power of the source operand minus 1.The source operand is located in register ST(0) and the result is also stored in ST(0).The value of the source operand must lie in the range –1.0 to +1.0. If the sourcevalue is outside this range, the result is undefined.The following table shows the results obtained when computing the exponentialvalue of various classes of numbers, assuming that neither overflow nor underflowoccurs.Table 3-21.
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