Volume 2A Instruction Set Reference A-M (794101), страница 59
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The source operand can be a generalpurpose register or a memory location. The action of this instruction depends on theoperand size (dividend/divisor). Division using 64-bit operand is available only in64-bit mode.Non-integral results are truncated (chopped) towards 0. The remainder is always lessthan the divisor in magnitude. Overflow is indicated with the #DE (divide error)exception rather than with the CF flag.3-310 Vol. 2ADIV—Unsigned DivideINSTRUCTION SET REFERENCE, A-MIn 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.Rprefix permits access to additional registers (R8-R15).
Use of the REX.W prefixpromotes operation to 64 bits. In 64-bit mode when REX.W is applied, the instructiondivides the unsigned value in RDX:RAX by the source operand and stores thequotient in RAX, the remainder in RDX.See the summary chart at the beginning of this section for encoding data and limits.See Table 3-20.Table 3-20. DIV ActionOperand SizeDividendDivisorQuotientRemainderMaximumQuotientWord/byteAXr/m8ALAH255Doubleword/wordDX:AXr/m16AXDX65,535Quadword/doublewordEDX:EAXr/m32EAXEDX232 − 1Doublequadword/RDX:RAXr/m64RAXRDX264 − 1quadwordOperationIF SRC = 0THEN #DE; FI; (* Divide Error *)IF OperandSize = 8 (* Word/Byte Operation *)THENtemp ← AX / SRC;IF temp > FFHTHEN #DE; (* Divide error *)ELSEAL ← temp;AH ← AX MOD SRC;FI;ELSE IF OperandSize = 16 (* Doubleword/word operation *)THENtemp ← DX:AX / SRC;IF temp > FFFFHTHEN #DE; (* Divide error *)ELSEAX ← temp;DX ← DX:AX MOD SRC;FI;FI;ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)THENtemp ← EDX:EAX / SRC;DIV—Unsigned DivideVol.
2A 3-311INSTRUCTION SET REFERENCE, A-MIF temp > FFFFFFFFHTHEN #DE; (* Divide error *)ELSEEAX ← temp;EDX ← EDX:EAX MOD SRC;FI;FI;ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)THENtemp ← RDX:RAX / SRC;IF temp > FFFFFFFFFFFFFFFFHTHEN #DE; (* Divide error *)ELSERAX ← temp;RDX ← RDX:RAX MOD SRC;FI;FI;FI;Flags AffectedThe CF, OF, SF, ZF, AF, and PF flags are undefined.Protected Mode Exceptions#DEIf the source operand (divisor) is 0#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the quotient is too large for the designated register.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#DEIf the source operand (divisor) is 0.If the quotient is too large for the designated register.#GP3-312 Vol.
2AIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.DIV—Unsigned DivideINSTRUCTION SET REFERENCE, A-MIf the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#DEIf the source operand (divisor) is 0.If the quotient is too large for the designated register.#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#DEIf the source operand (divisor) is 0#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.If the quotient is too large for the designated register.DIV—Unsigned DivideVol.
2A 3-313INSTRUCTION SET REFERENCE, A-MDIVPD—Divide Packed Double-Precision Floating-Point ValuesOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F 5E /rDIVPD xmm1,xmm2/m128AValidValidDivide packed doubleprecision floating-pointvalues in xmm1 by packeddouble-precision floatingpoint values xmm2/m128.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionPerforms a SIMD divide of the two packed double-precision floating-point values inthe destination operand (first operand) by the two packed double-precision floatingpoint values in the source operand (second operand), and stores the packed doubleprecision floating-point results in the destination operand.
The source operand canbe an XMM register or a 128-bit memory location. The destination operand is an XMMregister. See Chapter 11 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an overview of a SIMD double-precision floating-pointoperation.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[63:0] ← DEST[63:0] / (SRC[63:0]);DEST[127:64] ← DEST[127:64] / (SRC[127:64]);Intel C/C++ Compiler Intrinsic EquivalentDIVPD__m128d _mm_div_pd(__m128d a, __m128d b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.Protected Mode Exceptions#GP(0)3-314 Vol.
2AFor an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.DIVPD—Divide Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.DIVPD—Divide Packed Double-Precision Floating-Point ValuesVol.
2A 3-315INSTRUCTION SET REFERENCE, A-M#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.3-316 Vol. 2ADIVPD—Divide Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MDIVPS—Divide Packed Single-Precision Floating-Point ValuesOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 5E /rDIVPS xmm1,xmm2/m128AValidValidDivide packed singleprecision floating-pointvalues in xmm1 by packedsingle-precision floatingpoint values xmm2/m128.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionPerforms a SIMD divide of the four packed single-precision floating-point values inthe destination operand (first operand) by the four packed single-precision floatingpoint values in the source operand (second operand), and stores the packed singleprecision floating-point results in the destination operand.
The source operand canbe an XMM register or a 128-bit memory location. The destination operand is an XMMregister. See Chapter 10 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an overview of a SIMD single-precision floating-pointoperation.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← DEST[31:0] / (SRC[31:0]);DEST[63:32] ← DEST[63:32] / (SRC[63:32]);DEST[95:64] ← DEST[95:64] / (SRC[95:64]);DEST[127:96] ← DEST[127:96] / (SRC[127:96]);Intel C/C++ Compiler Intrinsic EquivalentDIVPS__m128 _mm_div_ps(__m128 a, __m128 b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.DIVPS—Divide Packed Single-Precision Floating-Point ValuesVol.
2A 3-317INSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.3-318 Vol.
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