Volume 2A Instruction Set Reference A-M (794101), страница 55
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The source operand can be ageneral-purpose register or a memory location. The destination operand is an XMMregister. The result is stored in the low doubleword of the destination operand, andthe upper three doublewords are left unchanged. When a conversion is inexact, thevalue returned is rounded according to the rounding control bits in the MXCSRregister.In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,R8-R15) when used with a REX.R prefix.
Use of the REX.W prefix promotes theinstruction to 64-bit operands. See the summary chart at the beginning of thissection for encoding data and limits.OperationIF 64-Bit Mode And OperandSize = 64THENDEST[31:0] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);(* DEST[127:32] unchanged *)ELSEDEST[31:0] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);(* DEST[127:32] unchanged *)FI;3-274 Vol. 2ACVTSI2SS—Convert Dword Integer to Scalar Single-Precision FP ValueINSTRUCTION SET REFERENCE, A-MIntel C/C++ Compiler Intrinsic EquivalentCVTSI2SS__m128 _mm_cvtsi32_ss(__m128 a, int b)SIMD Floating-Point ExceptionsPrecision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.CVTSI2SS—Convert Dword Integer to Scalar Single-Precision FP ValueVol.
2A 3-275INSTRUCTION SET REFERENCE, A-M#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)3-276 Vol. 2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTSI2SS—Convert Dword Integer to Scalar Single-Precision FP ValueINSTRUCTION SET REFERENCE, A-MCVTSS2SD—Convert Scalar Single-Precision FP Value to Scalar DoublePrecision FP ValueOpcodeInstructionOp/EnF3 0F 5A /rCVTSS2SD xmm1, Axmm2/m3264-BitModeCompat/ DescriptionLeg ModeValidValidConvert one single-precisionfloating-point value inxmm2/m32 to one doubleprecision floating-pointvalue in xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts a single-precision floating-point value in the source operand (secondoperand) to a double-precision floating-point value in the destination operand (firstoperand).
The source operand can be an XMM register or a 32-bit memory location.The destination operand is an XMM register. When the source operand is an XMMregister, the single-precision floating-point value is contained in the low doublewordof the register. The result is stored in the low quadword of the destination operand,and the high quadword is left unchanged.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[63:0] ← Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);(* DEST[127:64] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentCVTSS2SD __m128d _mm_cvtss_sd(__m128d a, __m128 b)SIMD Floating-Point ExceptionsInvalid, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.CVTSS2SD—Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP ValueVol.
2A 3-277INSTRUCTION SET REFERENCE, A-M#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.3-278 Vol.
2ACVTSS2SD—Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP ValueINSTRUCTION SET REFERENCE, A-M#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception andCR4.OSXMMEXCPT[bit 10] = 0exception andCR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTSS2SD—Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP ValueVol.
2A 3-279INSTRUCTION SET REFERENCE, A-MCVTSS2SI—Convert Scalar Single-Precision FP Value to Dword IntegerOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF3 0F 2D /rCVTSS2SI r32,xmm/m32AValidValidConvert one single-precisionfloating-point value fromxmm/m32 to one signeddoubleword integer in r32.F3 REX.W 0F 2D CVTSS2SI r64,/rxmm/m32AValidN.E.Convert one single-precisionfloating-point value fromxmm/m32 to one signedquadword integer in r64.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts a single-precision floating-point value in the source operand (secondoperand) to a signed doubleword integer (or signed quadword integer if operand sizeis 64 bits) in the destination operand (first operand). The source operand can be anXMM register or a memory location.
The destination operand is a general-purposeregister. When the source operand is an XMM register, the single-precision floatingpoint value is contained in the low doubleword of the register.When a conversion is inexact, the value returned is rounded according to therounding control bits in the MXCSR register. If a converted result is larger than themaximum signed doubleword integer, the floating-point invalid exception is raised,and if this exception is masked, the indefinite integer value (80000000H) is returned.In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,R8-R15) when used with a REX.R prefix.
Use of the REX.W prefix promotes theinstruction to 64-bit operands. See the summary chart at the beginning of thissection for encoding data and limits.OperationIF 64-bit Mode and OperandSize = 64THENDEST[64:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);ELSEDEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);FI;3-280 Vol. 2ACVTSS2SI—Convert Scalar Single-Precision FP Value to Dword IntegerINSTRUCTION SET REFERENCE, A-MIntel C/C++ Compiler Intrinsic Equivalentint _mm_cvtss_si32(__m128d a)SIMD Floating-Point ExceptionsInvalid, Precision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.CVTSS2SI—Convert Scalar Single-Precision FP Value to Dword IntegerVol.
2A 3-281INSTRUCTION SET REFERENCE, A-M#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)3-282 Vol. 2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTSS2SI—Convert Scalar Single-Precision FP Value to Dword IntegerINSTRUCTION SET REFERENCE, A-MCVTTPD2DQ—Convert with Truncation Packed Double-Precision FPValues to Packed Dword IntegersOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F E6CVTTPD2DQxmm1,xmm2/m128AValidValidConvert two packed doubleprecision floating-pointvalues from xmm2/m128 totwo packed signeddoubleword integers inxmm1 using truncation.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed double-precision floating-point values in the source operand(second operand) to two packed signed doubleword integers in the destinationoperand (first operand).
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