Volume 2A Instruction Set Reference A-M (794101), страница 53
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2A 3-257INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.3-258 Vol. 2ACVTPS2DQ—Convert Packed Single-Precision FP Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-MCVTPS2PD—Convert Packed Single-Precision FP Values to PackedDouble-Precision FP ValuesOpcodeInstructionOp/En0F 5A /rCVTPS2PD xmm1, Axmm2/m6464-BitModeCompat/ DescriptionLeg ModeValidValidConvert two packed singleprecision floating-pointvalues in xmm2/m64 to twopacked double-precisionfloating-point values inxmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed single-precision floating-point values in the source operand(second operand) to two packed double-precision floating-point values in the destination operand (first operand).The source operand can be an XMM register or a 64-bit memory location.
The destination operand is an XMM register. When the source operand is an XMM register, thepacked single-precision floating-point values are contained in the low quadword ofthe register.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[63:0] ← Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);DEST[127:64] ← Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32]);Intel C/C++ Compiler Intrinsic EquivalentCVTPS2PD__m128d _mm_cvtps_pd(__m128 a)SIMD Floating-Point ExceptionsInvalid, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.CVTPS2PD—Convert Packed Single-Precision FP Values to Packed Double-Precision FPValuesVol. 2A 3-259INSTRUCTION SET REFERENCE, A-M#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.3-260 Vol.
2ACVTPS2PD—Convert Packed Single-Precision FP Values to Packed Double-Precision FPValuesINSTRUCTION SET REFERENCE, A-M#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTPS2PD—Convert Packed Single-Precision FP Values to Packed Double-Precision FPValuesVol. 2A 3-261INSTRUCTION SET REFERENCE, A-MCVTPS2PI—Convert Packed Single-Precision FP Values to PackedDword IntegersOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 2D /rCVTPS2PI mm,xmm/m64AValidValidConvert two packed singleprecision floating-pointvalues from xmm/m64 totwo packed signeddoubleword integers in mm.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed single-precision floating-point values in the source operand(second operand) to two packed signed doubleword integers in the destinationoperand (first operand).The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an MMX technology register. When the source operand is an XMMregister, the two single-precision floating-point values are contained in the low quadword of the register. When a conversion is inexact, the value returned is roundedaccording to the rounding control bits in the MXCSR register. If a converted result islarger than the maximum signed doubleword integer, the floating-point invalidexception is raised, and if this exception is masked, the indefinite integer value(80000000H) is returned.CVTPS2PI causes a transition from x87 FPU to MMX technology operation (that is, thex87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s[valid]).
If this instruction is executed while an x87 FPU floating-point exception ispending, the exception is handled before the CVTPS2PI instruction is executed.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);Intel C/C++ Compiler Intrinsic EquivalentCVTPS2PI __m64 _mm_cvtps_pi32(__m128 a)3-262 Vol. 2ACVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsInvalid, Precision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#MFIf there is a pending x87 FPU exception.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword IntegersVol.
2A 3-263INSTRUCTION SET REFERENCE, A-M#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)3-264 Vol.
2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-MCVTSD2SI—Convert Scalar Double-Precision FP Value to IntegerOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF2 0F 2D /rCVTSD2SI r32,xmm/m64AValidValidConvert one doubleprecision floating-pointvalue from xmm/m64 toone signed doublewordinteger r32.F2 REX.W 0F2D /rCVTSD2SI r64,xmm/m64AValidN.E.Convert one doubleprecision floating-pointvalue from xmm/m64 toone signed quadwordinteger sign-extended intor64.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts a double-precision floating-point value in the source operand (secondoperand) to a signed doubleword integer in the destination operand (first operand).The source operand can be an XMM register or a 64-bit memory location.
The destination operand is a general-purpose register. When the source operand is an XMMregister, the double-precision floating-point value is contained in the low quadword ofthe register.When a conversion is inexact, the value returned is rounded according to therounding control bits in the MXCSR register. If a converted result is larger than themaximum signed doubleword integer, the floating-point invalid exception is raised,and if this exception is masked, the indefinite integer value (80000000H) is returned.In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes theinstruction to 64-bit operation.
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