Volume 2A Instruction Set Reference A-M (794101), страница 50
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2A 3-233INSTRUCTION SET REFERENCE, A-MTEMP6[31-0] Å TEMP5[39-0] MOD2 11EDC6F41HDEST[31-0] Å BIT_REFLECT (TEMP6[31-0])DEST[63-32] Å 00000000HCRC32 instruction for 8-bit source operand and 32-bit destination operand:TEMP1[7-0] Å BIT_REFLECT8(SRC[7-0])TEMP2[31-0] Å BIT_REFLECT32 (DEST[31-0])TEMP3[39-0] Å TEMP1[7-0] << 32TEMP4[39-0] Å TEMP2[31-0] << 8TEMP5[39-0] Å TEMP3[39-0] XOR TEMP4[39-0]TEMP6[31-0] Å TEMP5[39-0] MOD2 11EDC6F41HDEST[31-0] Å BIT_REFLECT (TEMP6[31-0])Flags AffectedNoneIntel C/C++ Compiler Intrinsic Equivalentunsigned int _mm_crc32_u8( unsigned int crc, unsigned char data )unsigned int _mm_crc32_u16( unsigned int crc, unsigned short data )unsigned int _mm_crc32_u32( unsigned int crc, unsigned int data )unsinged __int64 _mm_crc32_u64( unsinged __int64 crc, unsigned __int64 data )SIMD Floating Point ExceptionsNoneProtected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS or GS segments.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF (fault-code)For a page fault.#UDIf CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.If LOCK prefix is used.If REP (F3H) prefix is used.Real Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.3-234 Vol.
2ACRC32 — Accumulate CRC32 ValueINSTRUCTION SET REFERENCE, A-MIf LOCK prefix is used.If REP (F3H) prefix is used.Virtual 8086 Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF (fault-code)For a page fault.#UDIf CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.If LOCK prefix is used.If REP (F3H) prefix is used.Compatibility Mode ExceptionsSame exceptions as in Protected Mode.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#PF (fault-code)For a page fault.#UDIf CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.If LOCK prefix is used.If REP (F3H) prefix is used.CRC32 — Accumulate CRC32 ValueVol.
2A 3-235INSTRUCTION SET REFERENCE, A-MCVTDQ2PD—Convert Packed Dword Integers to Packed DoublePrecision FP ValuesOpcodeInstructionOp/EnF3 0F E6CVTDQ2PD xmm1, Axmm2/m6464-BitModeCompat/ DescriptionLeg ModeValidValidConvert two packed signeddoubleword integers fromxmm2/m128 to two packeddouble-precision floatingpoint values in xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed signed doubleword integers in the source operand (secondoperand) to two packed double-precision floating-point values in the destinationoperand (first operand).The source operand can be an XMM register or a 64-bit memory location.
The destination operand is an XMM register. When the source operand is an XMM register, thepacked integers are located in the low quadword of the register.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);DEST[127:64] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);Intel C/C++ Compiler Intrinsic EquivalentCVTDQ2PD__m128d _mm_cvtepi32_pd(__m128i a)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.3-236 Vol.
2ACVTDQ2PD—Convert Packed Dword Integers to Packed Double-Precision FP ValuesINSTRUCTION SET REFERENCE, A-M#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTDQ2PD—Convert Packed Dword Integers to Packed Double-Precision FP ValuesVol.
2A 3-237INSTRUCTION SET REFERENCE, A-MCVTDQ2PS—Convert Packed Dword Integers to Packed SinglePrecision FP ValuesOpcodeInstructionOp/En0F 5B /rCVTDQ2PS xmm1, Axmm2/m12864-BitModeCompat/ DescriptionLeg ModeValidValidConvert four packed signeddoubleword integers fromxmm2/m128 to four packedsingle-precision floatingpoint values in xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts four packed signed doubleword integers in the source operand (secondoperand) to four packed single-precision floating-point values in the destinationoperand (first operand).The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.
When a conversion is inexact, rounding isperformed according to the rounding control bits in the MXCSR register.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);DEST[63:32] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);DEST[95:64] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64]);DEST[127:96] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96]);Intel C/C++ Compiler Intrinsic EquivalentCVTDQ2PS__m128 _mm_cvtepi32_ps(__m128i a)SIMD Floating-Point ExceptionsPrecision.Protected Mode Exceptions#GP(0)3-238 Vol.
2AFor an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.CVTDQ2PS—Convert Packed Dword Integers to Packed Single-Precision FP ValuesINSTRUCTION SET REFERENCE, A-MIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.CVTDQ2PS—Convert Packed Dword Integers to Packed Single-Precision FP ValuesVol.
2A 3-239INSTRUCTION SET REFERENCE, A-M#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.3-240 Vol. 2ACVTDQ2PS—Convert Packed Dword Integers to Packed Single-Precision FP ValuesINSTRUCTION SET REFERENCE, A-MCVTPD2DQ—Convert Packed Double-Precision FP Values to PackedDword IntegersOpcodeInstructionOp/EnF2 0F E6CVTPD2DQ xmm1, Axmm2/m12864-BitModeCompat/ DescriptionLeg ModeValidValidConvert two packed doubleprecision floating-pointvalues from xmm2/m128 totwo packed signeddoubleword integers inxmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed double-precision floating-point values in the source operand(second operand) to two packed signed doubleword integers in the destinationoperand (first operand).The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register. The result is stored in the low quadword of thedestination operand and the high quadword is cleared to all 0s.When a conversion is inexact, the value returned is rounded according to therounding control bits in the MXCSR register. If a converted result is larger than themaximum signed doubleword integer, the floating-point invalid exception is raised,and if this exception is masked, the indefinite integer value (80000000H) is returned.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64]);DEST[127:64] ← 0000000000000000H;Intel C/C++ Compiler Intrinsic EquivalentCVTPD2DQ__m128i _mm_cvtpd_epi32(__m128d a)SIMD Floating-Point ExceptionsInvalid, Precision.CVTPD2DQ—Convert Packed Double-Precision FP Values to Packed Dword IntegersVol.
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