Volume 2A Instruction Set Reference A-M (794101), страница 51
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2A 3-241INSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.3-242 Vol.
2ACVTPD2DQ—Convert Packed Double-Precision FP Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.CVTPD2DQ—Convert Packed Double-Precision FP Values to Packed Dword IntegersVol.
2A 3-243INSTRUCTION SET REFERENCE, A-MCVTPD2PI—Convert Packed Double-Precision FP Values to PackedDword IntegersOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F 2D /rCVTPD2PI mm,xmm/m128AValidValidConvert two packed doubleprecision floating-pointvalues from xmm/m128 totwo packed signeddoubleword integers in mm.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed double-precision floating-point values in the source operand(second operand) to two packed signed doubleword integers in the destinationoperand (first operand).The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX technology register.When a conversion is inexact, the value returned is rounded according to therounding control bits in the MXCSR register.
If a converted result is larger than themaximum signed doubleword integer, the floating-point invalid exception is raised,and if this exception is masked, the indefinite integer value (80000000H) is returned.This instruction causes a transition from x87 FPU to MMX technology operation (thatis, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all0s [valid]). If this instruction is executed while an x87 FPU floating-point exception ispending, the exception is handled before the CVTPD2PI instruction is executed.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);Intel C/C++ Compiler Intrinsic EquivalentCVTPD1PI3-244 Vol.
2A__m64 _mm_cvtpd_pi32(__m128d a)CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsInvalid, Precision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#MFIf there is a pending x87 FPU exception.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword IntegersVol.
2A 3-245INSTRUCTION SET REFERENCE, A-M#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#MFIf there is a pending x87 FPU exception.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.3-246 Vol.
2ACVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-MCVTPD2PS—Convert Packed Double-Precision FP Values to PackedSingle-Precision FP ValuesOpcodeInstructionOp/En66 0F 5A /rCVTPD2PS xmm1, Axmm2/m12864-BitModeCompat/ DescriptionLeg ModeValidValidConvert two packed doubleprecision floating-pointvalues in xmm2/m128 totwo packed single-precisionfloating-point values inxmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed double-precision floating-point values in the source operand(second operand) to two packed single-precision floating-point values in the destination operand (first operand).The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register. The result is stored in the low quadword of thedestination operand, and the high quadword is cleared to all 0s. When a conversionis inexact, the value returned is rounded according to the rounding control bits in theMXCSR register.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);DEST[63:32] ← Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64]);DEST[127:64] ← 0000000000000000H;Intel C/C++ Compiler Intrinsic EquivalentCVTPD2PS__m128 _mm_cvtpd_ps(__m128d a)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.CVTPD2PS—Convert Packed Double-Precision FP Values to Packed Single-Precision FPValuesVol.
2A 3-247INSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.3-248 Vol.
2ACVTPD2PS—Convert Packed Double-Precision FP Values to Packed Single-Precision FPValuesINSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.CVTPD2PS—Convert Packed Double-Precision FP Values to Packed Single-Precision FPValuesVol. 2A 3-249INSTRUCTION SET REFERENCE, A-MCVTPI2PD—Convert Packed Dword Integers to Packed DoublePrecision FP ValuesOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F 2A /rCVTPI2PD xmm,mm/m64*AValidValidConvert two packed signeddoubleword integers frommm/mem64 to two packeddouble-precision floatingpoint values in xmm.NOTES:*Operation is different for different operand sets; see the Description section.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed signed doubleword integers in the source operand (secondoperand) to two packed double-precision floating-point values in the destinationoperand (first operand).The source operand can be an MMX technology register or a 64-bit memory location.The destination operand is an XMM register.
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