Volume 2A Instruction Set Reference A-M (794101), страница 46
Текст из файла (страница 46)
Integrate the fields into a display using the following rule:IF Family_ID ≠ 0FHTHEN Displayed_Family = Family_ID;ELSE Displayed_Family = Extended_Family_ID + Family_ID;(* Right justify and zero-extend 4-bit field. *)FI;(* Show Display_Family as HEX field. *)The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH.Integrate the field into a display using the following rule:IF (Family_ID = 06H or Family_ID = 0FH)THEN Displayed_Model = (Extended_Model_ID << 4) + Model_ID;(* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*)ELSE Displayed_Model = Model_ID;FI;(* Show Display_Model as HEX field.
*)INPUT EAX = 1: Returns Additional Information in EBXWhen CPUID executes with EAX set to 1, additional information is returned to theEBX register:•Brand index (low byte of EBX) — this number provides an entry into a brandstring table that contains brand strings for IA-32 processors. More informationabout this field is provided later in this section.•CLFLUSH instruction cache line size (second byte of EBX) — this numberindicates the size of the cache line flushed with CLFLUSH instruction in 8-byteincrements. This field was introduced in the Pentium 4 processor.CPUID—CPU IdentificationVol.
2A 3-209INSTRUCTION SET REFERENCE, A-M•Local APIC ID (high byte of EBX) — this number is the 8-bit ID that is assigned tothe local APIC on the processor during power up. This field was introduced in thePentium 4 processor.INPUT EAX = 1: Returns Feature Information in ECX and EDXWhen CPUID executes with EAX set to 1, feature information is returned in ECX andEDX.••Figure 3-6 and Table 3-15 show encodings for ECX.Figure 3-7 and Table 3-16 show encodings for EDX.For all feature flags, a 1 indicates that the feature is supported.
Use Intel to properlyinterpret feature flags.NOTESoftware must confirm that a processor feature is present usingfeature flags returned by CPUID prior to using the feature. Softwareshould not depend on future offerings retaining all features.3-210 Vol. 2ACPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-M31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 10ECX 0AVXOSXSAVEXSAVEAESPOPCNTMOVBEx2APICSSE4_2 — SSE4.2SSE4_1 — SSE4.1DCA — Direct Cache AccessPDCM — Perf/Debug Capability MSRxTPR Update ControlCMPXCHG16BFMA — Fused Multiply AddCNXT-ID — L1 Context IDSSSE3 — SSSE3 ExtensionsTM2 — Thermal Monitor 2EST — Enhanced Intel SpeedStep® TechnologySMX — Safer Mode ExtensionsVMX — Virtual Machine ExtensionsDS-CPL — CPL Qualified Debug StoreMONITOR — MONITOR/MWAITDTES64 — 64-bit DS AreaPCLMULQDQ — Carryless MultiplicationSSE3 — SSE3 ExtensionsReservedOM16524bFigure 3-6.
Feature Information Returned in the ECX RegisterTable 3-15. Feature Information Returned in the ECX RegisterBit #MnemonicDescription0SSE3Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates theprocessor supports this technology.1PCLMULQDQPCLMULQDQ.
A value of 1 indicates the processor supports thePCLMULQDQ instruction2DTES6464-bit DS Area. A value of 1 indicates the processor supports DSarea using 64-bit layout3MONITORMONITOR/MWAIT. A value of 1 indicates the processor supportsthis feature.CPUID—CPU IdentificationVol. 2A 3-211INSTRUCTION SET REFERENCE, A-MTable 3-15. Feature Information Returned in the ECX Register (Contd.)Bit #MnemonicDescription4DS-CPLCPL Qualified Debug Store. A value of 1 indicates the processorsupports the extensions to the Debug Store feature to allow forbranch message storage qualified by CPL.5VMXVirtual Machine Extensions. A value of 1 indicates that theprocessor supports this technology6SMXSafer Mode Extensions. A value of 1 indicates that the processorsupports this technology. See Chapter 6, “Safer Mode ExtensionsReference”.7ESTEnhanced Intel SpeedStep® technology.
A value of 1 indicatesthat the processor supports this technology.8TM2Thermal Monitor 2. A value of 1 indicates whether the processorsupports this technology.9SSSE3A value of 1 indicates the presence of the SupplementalStreaming SIMD Extensions 3 (SSSE3). A value of 0 indicates theinstruction extensions are not present in the processor10CNXT-IDL1 Context ID. A value of 1 indicates the L1 data cache mode canbe set to either adaptive mode or shared mode. A value of 0indicates this feature is not supported.
See definition of theIA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode)for details.12-11ReservedReserved13CMPXCHG16BCMPXCHG16B Available. A value of 1 indicates that the feature isavailable. See the “CMPXCHG8B/CMPXCHG16B—Compare andExchange Bytes” section in this chapter for a description.14xTPR UpdateControlxTPR Update Control. A value of 1 indicates that the processorsupports changing IA32_MISC_ENABLES[bit 23].15PDCMPerfmon and Debug Capability: A value of 1 indicates theprocessor supports the performance and debug feature indicationMSR IA32_PERF_CAPABILITIES.16ReservedReserved17PCIDProcess-context identifiers. A value of 1 indicates that theprocessor supports PCIDs and that software may set CR4.PCIDEto 1.18DCAA value of 1 indicates the processor supports the ability toprefetch data from a memory mapped device.19SSE4.1A value of 1 indicates that the processor supports SSE4.1.20SSE4.2A value of 1 indicates that the processor supports SSE4.2.21x2APICA value of 1 indicates that the processor supports x2APICfeature.3-212 Vol.
2ACPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MTable 3-15. Feature Information Returned in the ECX Register (Contd.)Bit #MnemonicDescription22MOVBEA value of 1 indicates that the processor supports MOVBEinstruction.23POPCNTA value of 1 indicates that the processor supports the POPCNTinstruction.24ReservedReserved25AESNIA value of 1 indicates that the processor supports the AESNIinstruction extensions.26XSAVEA value of 1 indicates that the processor supports theXSAVE/XRSTOR processor extended states feature, theXSETBV/XGETBV instructions, and theXFEATURE_ENABLED_MASK register (XCR0).27OSXSAVEA value of 1 indicates that the OS has enabled XSETBV/XGETBVinstructions to access the XFEATURE_ENABLED_MASK register(XCR0), and support for processor extended state managementusing XSAVE/XRSTOR.28AVXA value of 1 indicates the processor supports the AVX instructionextensions.30 - 29ReservedReserved31Not UsedAlways returns 0CPUID—CPU IdentificationVol.
2A 3-213INSTRUCTION SET REFERENCE, A-M (';3%(±3HQG%UN(170±7KHUP0RQLWRU+77±0XOWLWKUHDGLQJ66±6HOI6QRRS66(±66(([WHQVLRQV66(±66(([WHQVLRQV);65±);6$9();5672500;±00;7HFKQRORJ\$&3,±7KHUPDO0RQLWRUDQG&ORFN&WUO'6±'HEXJ6WRUH&/)6+±&)/86+LQVWUXFWLRQ361±3URFHVVRU6HULDO1XPEHU36(±3DJH6L]H([WHQVLRQ3$7±3DJH$WWULEXWH7DEOH&029±&RQGLWLRQDO0RYH&RPSDUH,QVWUXFWLRQ0&$±0DFKLQH&KHFN$UFKLWHFWXUH3*(±37(*OREDO%LW0755±0HPRU\7\SH5DQJH5HJLVWHUV6(3±6<6(17(5DQG6<6(;,7$3,&±$3,&RQ&KLS&;±&03;&+*%,QVW0&(±0DFKLQH&KHFN([FHSWLRQ3$(±3K\VLFDO$GGUHVV([WHQVLRQV065±5'065DQG:50656XSSRUW76&±7LPH6WDPS&RXQWHU36(±3DJH6L]H([WHQVLRQV'(±'HEXJJLQJ([WHQVLRQV90(±9LUWXDO0RGH(QKDQFHPHQW)38±[)38RQ&KLS5HVHUYHG20Figure 3-7. Feature Information Returned in the EDX Register3-214 Vol.
2ACPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MTable 3-16. More on Feature Information Returned in the EDX RegisterBit #MnemonicDescription0FPUFloating Point Unit On-Chip. The processor contains an x87 FPU.1VMEVirtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,including CR4.VME for controlling the feature, CR4.PVI for protected modevirtual interrupts, software interrupt indirection, expansion of the TSS withthe software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.2DEDebugging Extensions. Support for I/O breakpoints, including CR4.DE forcontrolling the feature, and optional trapping of accesses to DR4 and DR5.3PSEPage Size Extension.
Large pages of size 4 MByte are supported, includingCR4.PSE for controlling the feature, the defined dirty bit in PDE (PageDirectory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs.4TSCTime Stamp Counter. The RDTSC instruction is supported, including CR4.TSDfor controlling privilege.5MSRModel Specific Registers RDMSR and WRMSR Instructions.
The RDMSR andWRMSR instructions are supported. Some of the MSRs are implementationdependent.6PAEPhysical Address Extension. Physical addresses greater than 32 bits aresupported: extended page table entry formats, an extra level in the pagetranslation tables is defined, 2-MByte pages are supported instead of 4Mbyte pages if PAE bit is 1.7MCEMachine Check Exception. Exception 18 is defined for Machine Checks,including CR4.MCE for controlling the feature. This feature does not definethe model-specific implementations of machine-check error logging,reporting, and processor shutdowns.
Machine Check exception handlers mayhave to depend on processor version to do model specific processing of theexception, or test for the presence of the Machine Check feature.8CX8CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits)instruction is supported (implicitly locked and atomic).9APICAPIC On-Chip. The processor contains an Advanced Programmable InterruptController (APIC), responding to memory mapped commands in the physicaladdress range FFFE0000H to FFFE0FFFH (by default - some processorspermit the APIC to be relocated).10ReservedReserved11SEPSYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT andassociated MSRs are supported.12MTRRMemory Type Range Registers. MTRRs are supported.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
