Volume 2A Instruction Set Reference A-M (794101), страница 42
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2A 3-183INSTRUCTION SET REFERENCE, A-M#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)3-184 Vol.
2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CMPSS—Compare Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MCMPXCHG—Compare and ExchangeOpcodeInstruction0F B0/rOp/En64-BitModeCompat/ DescriptionLeg ModeCMPXCHG r/m8, r8 AValidValid*Compare AL with r/m8. Ifequal, ZF is set and r8 isloaded into r/m8. Else, clearZF and load r/m8 into AL.REX + 0F B0/rCMPXCHGr/m8**,r8AValidN.E.Compare AL with r/m8. Ifequal, ZF is set and r8 isloaded into r/m8. Else, clearZF and load r/m8 into AL.0F B1/rCMPXCHG r/m16,r16AValidValid*Compare AX with r/m16. Ifequal, ZF is set and r16 isloaded into r/m16. Else,clear ZF and load r/m16 intoAX.0F B1/rCMPXCHG r/m32,r32AValidValid*Compare EAX with r/m32.
Ifequal, ZF is set and r32 isloaded into r/m32. Else,clear ZF and load r/m32 intoEAX.REX.W + 0FB1/rCMPXCHG r/m64,r64AValidN.E.Compare RAX with r/m64. Ifequal, ZF is set and r64 isloaded into r/m64. Else,clear ZF and load r/m64 intoRAX.NOTES:* See the IA-32 Architecture Compatibility section below.** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r, w)ModRM:reg (r)NANADescriptionCompares the value in the AL, AX, EAX, or RAX register with the first operand (destination operand). If the two values are equal, the second operand (source operand) isloaded into the destination operand.
Otherwise, the destination operand is loadedinto the AL, AX, EAX or RAX register. RAX register is available only in 64-bit mode.CMPXCHG—Compare and ExchangeVol. 2A 3-185INSTRUCTION SET REFERENCE, A-MThis instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically. To simplify the interface to the processor’s bus, the destinationoperand receives a write cycle without regard to the result of the comparison.
Thedestination operand is written back if the comparison fails; otherwise, the sourceoperand is written into the destination. (The processor never produces a locked readwithout also producing a locked write.)In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.Rprefix permits access to additional registers (R8-R15). Use of the REX.W prefixpromotes operation to 64 bits. See the summary chart at the beginning of thissection for encoding data and limits.IA-32 Architecture CompatibilityThis instruction is not supported on Intel processors earlier than the Intel486 processors.Operation(* Accumulator = AL, AX, EAX, or RAX depending on whether a byte, word, doubleword, orquadword comparison is being performed *)IF accumulator = DESTTHENZF ← 1;DEST ← SRC;ELSEZF ← 0;accumulator ← DEST;FI;Flags AffectedThe ZF flag is set if the values in the destination operand and register AL, AX, or EAXare equal; otherwise it is cleared.
The CF, PF, AF, SF, and OF flags are set according tothe results of the comparison operation.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.3-186 Vol. 2ACMPXCHG—Compare and ExchangeINSTRUCTION SET REFERENCE, A-M#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.CMPXCHG—Compare and ExchangeVol.
2A 3-187INSTRUCTION SET REFERENCE, A-MCMPXCHG8B/CMPXCHG16B—Compare and Exchange BytesOpcodeInstruction0F C7 /1 m64REX.W + 0F C7/1 m128Op/En64-BitModeCompat/ DescriptionLeg ModeCMPXCHG8B m64 AValidValid*Compare EDX:EAX withm64. If equal, set ZF andload ECX:EBX into m64. Else,clear ZF and load m64 intoEDX:EAX.CMPXCHG16Bm128ValidN.E.Compare RDX:RAX withm128. If equal, set ZF andload RCX:RBX into m128.Else, clear ZF and load m128into RDX:RAX.ANOTES:*See IA-32 Architecture Compatibility section below.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r, w)NANANADescriptionCompares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if operand sizeis 128 bits) with the operand (destination operand).
If the values are equal, the64-bit value in ECX:EBX (or 128-bit value in RCX:RBX) is stored in the destinationoperand. Otherwise, the value in the destination operand is loaded into EDX:EAX (orRDX:RAX). The destination operand is an 8-byte memory location (or 16-bytememory location if operand size is 128 bits). For the EDX:EAX and ECX:EBX registerpairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the loworder 32 bits of a 64-bit value. For the RDX:RAX and RCX:RBX register pairs, RDXand RCX contain the high-order 64 bits and RAX and RBX contain the low-order64bits of a 128-bit value.This instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.
To simplify the interface to the processor’s bus, the destinationoperand receives a write cycle without regard to the result of the comparison. Thedestination operand is written back if the comparison fails; otherwise, the sourceoperand is written into the destination. (The processor never produces a locked readwithout also producing a locked write.)In 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotesoperation to 128 bits. Note that CMPXCHG16B requires that the destination(memory) operand be 16-byte aligned. See the summary chart at the beginning ofthis section for encoding data and limits. For information on the CPUID flag that indicates CMPXCHG16B, see page 3-211.3-188 Vol. 2ACMPXCHG8B/CMPXCHG16B—Compare and Exchange BytesINSTRUCTION SET REFERENCE, A-MIA-32 Architecture CompatibilityThis instruction encoding is not supported on Intel processors earlier than thePentium processors.OperationIF (64-Bit Mode and OperandSize = 64)THENIF (RDX:RAX = DEST)ZF ← 1;DEST ← RCX:RBX;ELSEZF ← 0;RDX:RAX ← DEST;FIELSEIF (EDX:EAX = DEST)ZF ← 1;DEST ← ECX:EBX;ELSEZF ← 0;EDX:EAX ← DEST;FI;FI;Flags AffectedThe ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it iscleared.
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