Volume 2A Instruction Set Reference A-M (794101), страница 43
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The CF, PF, AF, SF, and OF flags are unaffected.Protected Mode Exceptions#UDIf the destination is not a memory operand.#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CMPXCHG8B/CMPXCHG16B—Compare and Exchange BytesVol. 2A 3-189INSTRUCTION SET REFERENCE, A-MReal-Address Mode Exceptions#UDIf the destination operand is not a memory location.#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.Virtual-8086 Mode Exceptions#UDIf the destination operand is not a memory location.#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand for CMPXCHG16B is not aligned on a 16-byteboundary.If CPUID.01H:ECX.CMPXCHG16B[bit 13] = 0.#UDIf the destination operand is not a memory location.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.3-190 Vol.
2ACMPXCHG8B/CMPXCHG16B—Compare and Exchange BytesINSTRUCTION SET REFERENCE, A-MCOMISD—Compare Scalar Ordered Double-Precision Floating-PointValues and Set EFLAGSOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F 2F /rCOMISD xmm1,xmm2/m64AValidValidCompare low doubleprecision floating-pointvalues in xmm1 andxmm2/mem64 and set theEFLAGS flags accordingly.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r)ModRM:r/m (r)NANADescriptionCompares the double-precision floating-point values in the low quadwords ofoperand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, andCF flags in the EFLAGS register according to the result (unordered, greater than, lessthan, or equal).
The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memorylocation.The COMISD instruction differs from the UCOMISD instruction in that it signals aSIMD floating-point invalid operation exception (#I) when a source operand is eithera QNaN or SNaN. The UCOMISD instruction signals an invalid numeric exception onlyif a source operand is an SNaN.The EFLAGS register is not updated if an unmasked SIMD floating-point exception isgenerated.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationRESULT ← OrderedCompare(DEST[63:0] <> SRC[63:0]) {(* Set EFLAGS *) CASE (RESULT) OFUNORDERED:ZF,PF,CF ← 111;GREATER_THAN:ZF,PF,CF ← 000;LESS_THAN:ZF,PF,CF ← 001;EQUAL:ZF,PF,CF ← 100;ESAC;OF, AF, SF ← 0; }COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and SetEFLAGSVol.
2A 3-191INSTRUCTION SET REFERENCE, A-MIntel C/C++ Compiler Intrinsic Equivalentsint _mm_comieq_sd (__m128d a, __m128d b)int _mm_comilt_sd (__m128d a, __m128d b)int _mm_comile_sd (__m128d a, __m128d b)int _mm_comigt_sd (__m128d a, __m128d b)int _mm_comige_sd (__m128d a, __m128d b)int _mm_comineq_sd (__m128d a, __m128d b)SIMD Floating-Point ExceptionsInvalid (if SNaN or QNaN operands), Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.3-192 Vol.
2ACOMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and SetEFLAGSINSTRUCTION SET REFERENCE, A-MIf the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and SetEFLAGSVol.
2A 3-193INSTRUCTION SET REFERENCE, A-MCOMISS—Compare Scalar Ordered Single-Precision Floating-PointValues and Set EFLAGSOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 2F /rCOMISS xmm1,xmm2/m32AValidValidCompare low singleprecision floating-pointvalues in xmm1 andxmm2/mem32 and set theEFLAGS flags accordingly.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r)ModRM:r/m (r)NANADescriptionCompares the single-precision floating-point values in the low doublewords ofoperand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, andCF flags in the EFLAGS register according to the result (unordered, greater than, lessthan, or equal). The OF, SF, and AF flags in the EFLAGS register are set to 0.
Theunordered result is returned if either source operand is a NaN (QNaN or SNaN).Operand 1 is an XMM register; Operand 2 can be an XMM register or a 32 bit memorylocation.The COMISS instruction differs from the UCOMISS instruction in that it signals aSIMD floating-point invalid operation exception (#I) when a source operand is eithera QNaN or SNaN. The UCOMISS instruction signals an invalid numeric exception onlyif a source operand is an SNaN.The EFLAGS register is not updated if an unmasked SIMD floating-point exception isgenerated.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationRESULT ← OrderedCompare(SRC1[31:0] <> SRC2[31:0]) {(* Set EFLAGS *) CASE (RESULT) OFUNORDERED:ZF,PF,CF ← 111;GREATER_THAN:ZF,PF,CF ← 000;LESS_THAN:ZF,PF,CF ← 001;EQUAL:ZF,PF,CF ← 100;ESAC;OF,AF,SF ← 0; }3-194 Vol.
2ACOMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-MIntel C/C++ Compiler Intrinsic Equivalentsint _mm_comieq_ss (__m128 a, __m128 b)int _mm_comilt_ss (__m128 a, __m128 b)int _mm_comile_ss (__m128 a, __m128 b)int _mm_comigt_ss (__m128 a, __m128 b)int _mm_comige_ss (__m128 a, __m128 b)int _mm_comineq_ss (__m128 a, __m128 b)SIMD Floating-Point ExceptionsInvalid (if SNaN or QNaN operands), Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGSVol.
2A 3-195INSTRUCTION SET REFERENCE, A-MIf the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)3-196 Vol.
2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGSINSTRUCTION SET REFERENCE, A-MCPUID—CPU IdentificationOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F A2CPUIDAValidValidReturns processoridentification and featureinformation to the EAX,EBX, ECX, and EDXregisters, as determined byinput entered in EAX (insome cases, ECX as well).Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionThe ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction.
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