Volume 2A Instruction Set Reference A-M (794101), страница 38
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A condition code (cc) is associated with eachinstruction to indicate the condition being tested for. If the condition is not satisfied,a move is not performed and execution continues with the instruction following theCMOVcc instruction.These instructions can move 16-bit, 32-bit or 64-bit values from memory to ageneral-purpose register or from one general-purpose register to another. Conditional moves of 8-bit register operands are not supported.The condition for each CMOVcc mnemonic is given in the description column of theabove table. The terms “less” and “greater” are used for comparisons of signed integers and the terms “above” and “below” are used for unsigned integers.Because a particular state of the status flags can sometimes be interpreted in twoways, two mnemonics are defined for some opcodes.
For example, the CMOVA(conditional move if above) instruction and the CMOVNBE (conditional move if notbelow or equal) instruction are alternate mnemonics for the opcode 0F 47H.The CMOVcc instructions were introduced in P6 family processors; however, theseinstructions may not be supported by all IA-32 processors. Software can determine ifthe CMOVcc instructions are supported by checking the processor’s feature information with the CPUID instruction (see “CPUID—CPU Identification” in this chapter).In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.Rprefix permits access to additional registers (R8-R15).
Use of the REX.W prefixpromotes operation to 64 bits. See the summary chart at the beginning of thissection for encoding data and limits.Operationtemp ← SRCCMOVcc—Conditional MoveVol. 2A 3-155INSTRUCTION SET REFERENCE, A-MIF condition TRUETHENDEST ← temp;FI;ELSEIF (OperandSize == 32 and IA-32e mode active)THENDEST[63:32] ← 0;FI;FI;Flags AffectedNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.3-156 Vol.
2ACMOVcc—Conditional MoveINSTRUCTION SET REFERENCE, A-M#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.CMOVcc—Conditional MoveVol. 2A 3-157INSTRUCTION SET REFERENCE, A-MCMP—Compare Two OperandsOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode3C ibCMP AL, imm8DValidValidCompare imm8 with AL.3D iwCMP AX, imm16DValidValidCompare imm16 with AX.3D idCMP EAX, imm32DValidValidCompare imm32 with EAX.REX.W + 3D idCMP RAX, imm32DValidN.E.Compare imm32 signextended to 64-bits withRAX.80 /7 ibCMP r/m8, imm8CValidValidCompare imm8 with r/m8.*REX + 80 /7 ibCMP r/m8 , imm8CValidN.E.Compare imm8 with r/m8.81 /7 iwCMP r/m16,imm16CValidValidCompare imm16 withr/m16.81 /7 idCMP r/m32,imm32CValidValidCompare imm32 withr/m32.REX.W + 81 /7idCMP r/m64,imm32CValidN.E.Compare imm32 signextended to 64-bits withr/m64.83 /7 ibCMP r/m16, imm8CValidValidCompare imm8 with r/m16.83 /7 ibCMP r/m32, imm8CValidValidCompare imm8 with r/m32.REX.W + 83 /7ibCMP r/m64, imm8CValidN.E.Compare imm8 with r/m64.38 /rCMP r/m8, r8BValidValidCompare r8 with r/m8.**REX + 38 /rCMP r/m8 , r8BValidN.E.Compare r8 with r/m8.39 /rCMP r/m16, r16BValidValidCompare r16 with r/m16.39 /rCMP r/m32, r32BValidValidCompare r32 with r/m32.REX.W + 39 /rCMP r/m64,r64BValidN.E.Compare r64 with r/m64.3A /rCMP r8, r/m8AValidValidCompare r/m8 with r8.REX + 3A /rCMP r8*, r/m8*AValidN.E.Compare r/m8 with r8.3B /rCMP r16, r/m16AValidValidCompare r/m16 with r16.3B /rCMP r32, r/m32AValidValidCompare r/m32 with r32.REX.W + 3B /rCMP r64, r/m64AValidN.E.Compare r/m64 with r64.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.3-158 Vol.
2ACMP—Compare Two OperandsINSTRUCTION SET REFERENCE, A-MInstruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANABModRM:r/m (r, w)ModRM:reg (w)NANACModRM:r/m (r, w)imm8NANADAL/AX/EAX/RAXimm8NANADescriptionCompares the first source operand with the second source operand and sets thestatus flags in the EFLAGS register according to the results.
The comparison isperformed by subtracting the second operand from the first operand and then settingthe status flags in the same manner as the SUB instruction. When an immediatevalue is used as an operand, it is sign-extended to the length of the first operand.The condition codes used by the Jcc, CMOVcc, and SETcc instructions are based onthe results of a CMP instruction. Appendix B, “EFLAGS Condition Codes,” in theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, showsthe relationship of the status flags and the condition codes.In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.Rprefix permits access to additional registers (R8-R15).
Use of the REX.W prefixpromotes operation to 64 bits. See the summary chart at the beginning of thissection for encoding data and limits.Operationtemp ← SRC1 − SignExtend(SRC2);ModifyStatusFlags; (* Modify status flags in the same manner as the SUB instruction*)Flags AffectedThe CF, OF, SF, ZF, AF, and PF flags are set according to the result.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CMP—Compare Two OperandsVol.
2A 3-159INSTRUCTION SET REFERENCE, A-M#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-160 Vol.
2ACMP—Compare Two OperandsINSTRUCTION SET REFERENCE, A-MCMPPD—Compare Packed Double-Precision Floating-Point ValuesOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F C2 /r ibCMPPD xmm1,xmm2/m128, imm8AValidValidCompare packed doubleprecision floating-pointvalues in xmm2/m128 andxmm1 using imm8 ascomparison predicate.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)imm8NADescriptionPerforms a SIMD compare of the two packed double-precision floating-point values inthe source operand (second operand) and the destination operand (first operand)and returns the results of the comparison to the destination operand.
The comparison predicate operand (third operand) specifies the type of comparison performedon each of the pairs of packed values. The result of each comparison is a quadwordmask of all 1s (comparison true) or all 0s (comparison false).The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register. The comparison predicate operand is an 8-bitimmediate, the first 3 bits of which define the type of comparison to be made (seeTable 3-7).
Bits 3 through 7 of the immediate are reserved.Table 3-7. Comparison Predicate for CMPPD and CMPPS InstructionsPredicateimm8EncodingDescriptionRelation where:A Is 1st OperandB Is 2ndOperandEmulation Result ifNaNOperandQNaNOper-andSignalsInvalidEQ000BEqualA=BFalseNoLT001BLess-thanA<BFalseYesLE010BLess-than-or-equalA≤BFalseYesGreater thanA>BSwapOperands,Use LTFalseYesGreater-than-orequalA≥BSwapOperands,Use LEFalseYesCMPPD—Compare Packed Double-Precision Floating-Point ValuesVol. 2A 3-161INSTRUCTION SET REFERENCE, A-MTable 3-7. Comparison Predicate for CMPPD and CMPPS Instructions (Contd.)imm8EncodingDescriptionRelation where:A Is 1st OperandB Is 2ndOperandUNORD011BUnorderedA, B = UnorderedTrueNoNEQ100BNot-equalA≠BTrueNoNLT101BNot-less-thanNOT(A < B)TrueYesNLE110BNot-less-than-orequalNOT(A ≤ B)TrueYesNot-greater-thanNOT(A > B)SwapOperands,Use NLTTrueYesNot-greater-thanor-equalNOT(A ≥ B)SwapOperands,Use NLETrueYesOrderedA , B = OrderedFalseNoORD111BEmulation Result ifNaNOperandQNaNOper-andSignalsInvalidPredicateThe unordered relationship is true when at least one of the two source operandsbeing compared is a NaN; the ordered relationship is true when neither sourceoperand is a NaN.A subsequent computational instruction that uses the mask result in the destinationoperand as an input operand will not generate an exception, because a mask of all 0scorresponds to a floating-point value of +0.0 and a mask of all 1s corresponds to aQNaN.Note that the processor does not implement the greater-than, greater-than-orequal, not-greater-than, and not-greater-than-or-equal relations.
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