Volume 2A Instruction Set Reference A-M (794101), страница 40
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2A 3-169INSTRUCTION SET REFERENCE, A-M#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.3-170 Vol. 2ACMPPS—Compare Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MCMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeA6CMPS m8, m8AValidValidFor legacy mode, comparebyte at address DS:(E)SIwith byte at addressES:(E)DI; For 64-bit modecompare byte at address(R|E)SI to byte at address(R|E)DI.
The status flags areset accordingly.A7CMPS m16, m16AValidValidFor legacy mode, compareword at address DS:(E)SIwith word at addressES:(E)DI; For 64-bit modecompare word at address(R|E)SI with word at address(R|E)DI. The status flags areset accordingly.A7CMPS m32, m32AValidValidFor legacy mode, comparedword at address DS:(E)SI atdword at address ES:(E)DI;For 64-bit mode comparedword at address (R|E)SI atdword at address (R|E)DI.The status flags are setaccordingly.REX.W + A7CMPS m64, m64AValidN.E.Compares quadword ataddress (R|E)SI withquadword at address (R|E)DIand sets the status flagsaccordingly.A6CMPSBAValidValidFor legacy mode, comparebyte at address DS:(E)SIwith byte at addressES:(E)DI; For 64-bit modecompare byte at address(R|E)SI with byte at address(R|E)DI.
The status flags areset accordingly.CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsVol. 2A 3-171INSTRUCTION SET REFERENCE, A-MOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeA7CMPSWAValidValidFor legacy mode, compareword at address DS:(E)SIwith word at addressES:(E)DI; For 64-bit modecompare word at address(R|E)SI with word at address(R|E)DI. The status flags areset accordingly.A7CMPSDAValidValidFor legacy mode, comparedword at address DS:(E)SIwith dword at addressES:(E)DI; For 64-bit modecompare dword at address(R|E)SI with dword ataddress (R|E)DI.
The statusflags are set accordingly.REX.W + A7CMPSQAValidN.E.Compares quadword ataddress (R|E)SI withquadword at address (R|E)DIand sets the status flagsaccordingly.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionCompares the byte, word, doubleword, or quadword specified with the first sourceoperand with the byte, word, doubleword, or quadword specified with the secondsource operand and sets the status flags in the EFLAGS register according to theresults.Both source operands are located in memory. The address of the first source operandis read from DS:SI, DS:ESI or RSI (depending on the address-size attribute of theinstruction is 16, 32, or 64, respectively). The address of the second source operandis read from ES:DI, ES:EDI or RDI (again depending on the address-size attribute ofthe instruction is 16, 32, or 64).
The DS segment may be overridden with a segmentoverride prefix, but the ES segment cannot be overridden.At the assembly-code level, two forms of this instruction are allowed: the “explicitoperands” form and the “no-operands” form. The explicit-operands form (specifiedwith the CMPS mnemonic) allows the two source operands to be specified explicitly.3-172 Vol. 2ACMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsINSTRUCTION SET REFERENCE, A-MHere, the source operands should be symbols that indicate the size and location ofthe source values. This explicit-operand form is provided to allow documentation.However, note that the documentation provided by this form can be misleading.
Thatis, the source operand symbols must specify the correct type (size) of the operands(bytes, words, or doublewords, quadwords), but they do not have to specify thecorrect location. Locations of the source operands are always specified by theDS:(E)SI (or RSI) and ES:(E)DI (or RDI) registers, which must be loaded correctlybefore the compare string instruction is executed.The no-operands form provides “short forms” of the byte, word, and doublewordversions of the CMPS instructions. Here also the DS:(E)SI (or RSI) and ES:(E)DI (orRDI) registers are assumed by the processor to specify the location of the sourceoperands.
The size of the source operands is selected with the mnemonic: CMPSB(byte comparison), CMPSW (word comparison), CMPSD (doubleword comparison),or CMPSQ (quadword comparison using REX.W).After the comparison, the (E/R)SI and (E/R)DI registers increment or decrementautomatically according to the setting of the DF flag in the EFLAGS register. (If the DFflag is 0, the (E/R)SI and (E/R)DI register increment; if the DF flag is 1, the registersdecrement.) The registers increment or decrement by 1 for byte operations, by 2 forword operations, 4 for doubleword operations. If operand size is 64, RSI and RDIregisters increment by 8 for quadword operations.The CMPS, CMPSB, CMPSW, CMPSD, and CMPSQ instructions can be preceded by theREP prefix for block comparisons. More often, however, these instructions will beused in a LOOP construct that takes some action based on the setting of the statusflags before the next comparison is made. See “REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix” in Chapter 4 of the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 2B, for a description of theREP prefix.In 64-bit mode, the instruction’s default address size is 64 bits, 32 bit address size issupported using the prefix 67H.
Use of the REX.W prefix promotes doubleword operation to 64 bits (see CMPSQ). See the summary chart at the beginning of this sectionfor encoding data and limits.Operationtemp SRC1 - SRC2;SetStatusFlags(temp);IF (64-Bit Mode)THENIF (Byte comparison)THEN IF DF = 0THEN(R|E)SI ← (R|E)SI + 1;(R|E)DI ← (R|E)DI + 1;ELSECMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsVol. 2A 3-173INSTRUCTION SET REFERENCE, A-M(R|E)SI ← (R|E)SI – 1;(R|E)DI ← (R|E)DI – 1;FI;ELSE IF (Word comparison)THEN IF DF = 0THEN(R|E)SI ← (R|E)SI + 2;(R|E)DI ← (R|E)DI + 2;ELSE(R|E)SI ← (R|E)SI – 2;(R|E)DI ← (R|E)DI – 2;FI;ELSE IF (Doubleword comparison)THEN IF DF = 0THEN(R|E)SI ← (R|E)SI + 4;(R|E)DI ← (R|E)DI + 4;ELSE(R|E)SI ← (R|E)SI – 4;(R|E)DI ← (R|E)DI – 4;FI;ELSE (* Quadword comparison *)THEN IF DF = 0(R|E)SI ← (R|E)SI + 8;(R|E)DI ← (R|E)DI + 8;ELSE(R|E)SI ← (R|E)SI – 8;(R|E)DI ← (R|E)DI – 8;FI;FI;ELSE (* Non-64-bit Mode *)IF (byte comparison)THEN IF DF = 0THEN(E)SI ← (E)SI + 1;(E)DI ← (E)DI + 1;ELSE(E)SI ← (E)SI – 1;(E)DI ← (E)DI – 1;FI;ELSE IF (Word comparison)THEN IF DF = 0(E)SI ← (E)SI + 2;3-174 Vol.
2ACMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsINSTRUCTION SET REFERENCE, A-M(E)DI ← (E)DI + 2;ELSE(E)SI ← (E)SI – 2;(E)DI ← (E)DI – 2;FI;ELSE (* Doubleword comparison *)THEN IF DF = 0(E)SI ← (E)SI + 4;(E)DI ← (E)DI + 4;ELSE(E)SI ← (E)SI – 4;(E)DI ← (E)DI – 4;FI;FI;FI;Flags AffectedThe CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result of thecomparison.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsVol.
2A 3-175INSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-176 Vol.
2ACMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String OperandsINSTRUCTION SET REFERENCE, A-MCMPSD—Compare Scalar Double-Precision Floating-Point ValuesOpcodeInstructionOp/EnF2 0F C2 /r ibCMPSD xmm1,Axmm2/m64, imm864-BitModeCompat/ DescriptionLeg ModeValidValidCompare low doubleprecision floating-pointvalue in xmm2/m64 andxmm1 using imm8 ascomparison predicate.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)imm8NADescriptionCompares the low double-precision floating-point values in the source operand(second operand) and the destination operand (first operand) and returns the resultsof the comparison to the destination operand.
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