Volume 2A Instruction Set Reference A-M (794101), страница 44
Текст из файла (страница 44)
If a software procedure can set and clear this flag, the processor executing theprocedure supports the CPUID instruction. This instruction operates the same in non64-bit modes and 64-bit mode.CPUID returns processor identification and feature information in the EAX, EBX, ECX,and EDX registers.1 The instruction’s output is dependent on the contents of the EAXregister upon execution (in some cases, ECX as well). For example, the followingpseudocode loads EAX with 00H and causes CPUID to return a Maximum ReturnValue and the Vendor Identification String in the appropriate registers:MOV EAX, 00HCPUIDTable 3-12 shows information returned, depending on the initial value loaded into theEAX register. Table 3-13 shows the maximum CPUID input value recognized for eachfamily of IA-32 processors on which CPUID is implemented.Two types of information are returned: basic and extended function information.
If avalue entered for CPUID.EAX is higher than the maximum input value for basic orextended function for that processor then the data for the highest basic informationleaf is returned. For example, using the Intel Core i7 processor, the following is true:CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *)1. On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in allmodes.CPUID—CPU IdentificationVol.
2A 3-197INSTRUCTION SET REFERENCE, A-MCPUID.EAX = 0CH (* INVALID: Returns the same information as CPUID.EAX = 0BH. *)CPUID.EAX = 80000008H (* Returns linear/physical address size data. *)CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0BH. *)If a value entered for CPUID.EAX is less than or equal to the maximum input valueand the leaf is not supported on that processor then 0 is returned in all the registers.For example, using the Intel Core i7 processor, the following is true:CPUID.EAX = 07H (*Returns EAX=EBX=ECX=EDX=0. *)When CPUID returns the highest basic leaf information as a result of an invalid inputEAX value, any dependence on input ECX value in the basic leaf is honored.CPUID can be executed at any privilege level to serialize instruction execution.
Serializing instruction execution guarantees that any modifications to flags, registers,and memory for previous instructions are completed before the next instruction isfetched and executed.See also:“Serializing Instructions” in Chapter 8, “Multiple-Processor Management,” in theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A“Caching Translation Information” in Chapter 4, “Paging,” in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 3ATable 3-12. Information Returned by CPUID InstructionInitial EAXValueInformation Provided about the ProcessorBasic CPUID Information0HEAXEBXECXEDXMaximum Input Value for Basic CPUID Information (see Table 3-13)“Genu”“ntel”“ineI”01HEAXVersion Information: Type, Family, Model, and Stepping ID (seeFigure 3-5)EBXBits 7-0: Brand IndexBits 15-8: CLFLUSH line size (Value ∗ 8 = cache line size in bytes)Bits 23-16: Maximum number of addressable IDs for logical processorsin this physical package*.Bits 31-24: Initial APIC IDECXEDXFeature Information (see Figure 3-6 and Table 3-15)Feature Information (see Figure 3-7 and Table 3-16)NOTES:* The nearest power-of-2 integer that is not smaller than EBX[23:16]is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package.3-198 Vol.
2ACPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MTable 3-12. Information Returned by CPUID Instruction (Contd.)Initial EAXValueInformation Provided about the Processor02HEAXEBXECXEDXCache and TLB Information (see Table 3-17)Cache and TLB InformationCache and TLB InformationCache and TLB Information03HEAXEBXReserved.Reserved.ECXBits 00-31 of 96 bit processor serial number. (Available in Pentium IIIprocessor only; otherwise, the value in this register is reserved.)EDXBits 32-63 of 96 bit processor serial number.
(Available in Pentium IIIprocessor only; otherwise, the value in this register is reserved.)NOTES:Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use the PSN flag (returned usingCPUID) to check for PSN support before accessing the feature.See AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618) for more information on PSN.CPUID leaves > 3 < 80000000 are visible only whenIA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).Deterministic Cache Parameters Leaf04HNOTES:Leaf 04H output depends on the initial value in ECX.See also: “INPUT EAX = 4: Returns Deterministic Cache Parametersfor each level on page 3-221.EAXBits 4-0: Cache Type Field0 = Null - No more caches1 = Data Cache2 = Instruction Cache3 = Unified Cache4-31 = ReservedBits 7-5: Cache Level (starts at 1)Bits 8: Self Initializing cache level (does not need SW initialization)Bits 9: Fully Associative cacheBits 13-10: ReservedBits 25-14: Maximum number of addressable IDs for logical processorssharing this cache*, **Bits 31-26: Maximum number of addressable IDs for processor cores inthe physical package*, ***, ****CPUID—CPU IdentificationVol.
2A 3-199INSTRUCTION SET REFERENCE, A-MTable 3-12. Information Returned by CPUID Instruction (Contd.)Initial EAXValueInformation Provided about the ProcessorEBXBits 11-00: L = System Coherency Line Size*Bits 21-12: P = Physical Line partitions*Bits 31-22: W = Ways of associativity*ECXBits 31-00: S = Number of Sets*EDXBit 0: Write-Back Invalidate/Invalidate0 = WBINVD/INVD from threads sharing this cache acts upon lowerlevel caches for threads sharing this cache.1 = WBINVD/INVD is not guaranteed to act upon lower level cachesof non-originating threads sharing this cache.Bit 1: Cache Inclusiveness0 = Cache is not inclusive of lower cache levels.1 = Cache is inclusive of lower cache levels.Bit 2: Complex Cache Indexing0 = Direct mapped cache.1 = A complex function is used to index the cache, potentially usingall address bits.Bits 31-03: Reserved = 0NOTES:* Add one to the return value to get the result.** The nearest power-of-2 integer that is not smaller than (1 +EAX[25:14]) is the number of unique initial APIC IDs reserved foraddressing different logical processors sharing this cache*** The nearest power-of-2 integer that is not smaller than (1 +EAX[31:26]) is the number of unique Core_IDs reserved for addressing different processor cores in a physical package.
Core ID is a subset of bits of the initial APIC ID.****The returned value is constant for valid initial values in ECX. ValidECX values start from 0.MONITOR/MWAIT Leaf05H3-200 Vol. 2AEAXBits 15-00: Smallest monitor-line size in bytes (default is processor'smonitor granularity)Bits 31-16: Reserved = 0EBXBits 15-00: Largest monitor-line size in bytes (default is processor'smonitor granularity)Bits 31-16: Reserved = 0CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MTable 3-12. Information Returned by CPUID Instruction (Contd.)Initial EAXValueInformation Provided about the ProcessorECXBit 00: Enumeration of Monitor-Mwait extensions (beyond EAX andEBX registers) supportedBit 01: Supports treating interrupts as break-event for MWAIT, evenwhen interrupts disabledBits 31 - 02: ReservedEDXBits 03 - 00: Number of C0* sub C-states supported using MWaitBits 07 - 04: Number of C1* sub C-states supported using MWAITBits 11 - 08: Number of C2* sub C-states supported using MWAITBits 15 - 12: Number of C3* sub C-states supported using MWAITBits 19 - 16: Number of C4* sub C-states supported using MWAITBits 31 - 20: Reserved = 0NOTE:* The definition of C0 through C4 states for MWAIT extension are processor-specific C-states, not ACPI C-states.Thermal and Power Management Leaf06HEAXEBXBit 00: Digital temperature sensor is supported if setBit 01: Intel Turbo Boost Technology Available (see description ofIA32_MISC_ENABLES[38]).Bit 02: ARAT.
APIC-Timer-always-running feature is supported if set.Bits 31 - 03: ReservedBits 03 - 00: Number of Interrupt Thresholds in Digital Thermal SensorBits 31 - 04: ReservedECXBit 00: Hardware Coordination Feedback Capability (Presence ofIA32_MPERF and IA32_APERF). The capability to provide a measure ofdelivered processor performance (since last reset of the counters), asa percentage of expected processor performance at frequency specified in CPUID Brand StringBits 02 - 01: Reserved = 0Bit 03: The processor supports performance-energy bias preference ifCPUID.06H:ECX.SETBH[bit 3] is set and it also implies the presence of anew architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H)Bits 31 - 04: Reserved = 0EDXReserved = 0Direct Cache Access Information LeafCPUID—CPU IdentificationVol. 2A 3-201INSTRUCTION SET REFERENCE, A-MTable 3-12.
Information Returned by CPUID Instruction (Contd.)Initial EAXValue09HInformation Provided about the ProcessorEAXEBXECXEDXValue of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address1F8H)ReservedReservedReservedArchitectural Performance Monitoring Leaf0AHEAXBits 07 - 00: Version ID of architectural performance monitoringBits 15- 08: Number of general-purpose performance monitoringcounter per logical processorBits 23 - 16: Bit width of general-purpose, performance monitoringcounterBits 31 - 24: Length of EBX bit vector to enumerate architectural performance monitoring eventsEBXBit 0: Core cycle event not available if 1Bit 1: Instruction retired event not available if 1Bit 2: Reference cycles event not available if 1Bit 3: Last-level cache reference event not available if 1Bit 4: Last-level cache misses event not available if 1Bit 5: Branch instruction retired event not available if 1Bit 6: Branch mispredict retired event not available if 1Bits 31- 07: Reserved = 0ECXReserved = 0EDXBits 04 - 00: Number of fixed-function performance counters (if Version ID > 1)Bits 12- 05: Bit width of fixed-function performance counters (if Version ID > 1)Reserved = 0Extended Topology Enumeration Leaf0BH3-202 Vol.
2ANOTES:Most of Leaf 0BH output depends on the initial value in ECX.EDX output do not vary with initial value in ECX.ECX[7:0] output always reflect initial value in ECX.All other output value for an invalid initial value in ECX are 0.Leaf 0BH exists if EBX[15:0] is not zero.CPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MTable 3-12. Information Returned by CPUID Instruction (Contd.)Initial EAXValueInformation Provided about the ProcessorEAXBits 4-0: Number of bits to shift right on x2APIC ID to get a uniquetopology ID of the next level type*. All logical processors with thesame next level ID share current level.Bits 31-5: Reserved.EBXBits 15 - 00: Number of logical processors at this level type.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
