Volume 2A Instruction Set Reference A-M (794101), страница 47
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The MTRRcap MSRcontains feature bits that describe what memory types are supported, howmany variable MTRRs are supported, and whether fixed MTRRs aresupported.CPUID—CPU IdentificationVol. 2A 3-215INSTRUCTION SET REFERENCE, A-MTable 3-16. More on Feature Information Returned in the EDX Register (Contd.)Bit #MnemonicDescription13PGEPage Global Bit. The global bit is supported in paging-structure entries thatmap a page, indicating TLB entries that are common to different processesand need not be flushed. The CR4.PGE bit controls this feature.14MCAMachine Check Architecture.
The Machine Check Architecture, whichprovides a compatible mechanism for error reporting in P6 family, Pentium4, Intel Xeon processors, and future processors, is supported. The MCG_CAPMSR contains feature bits describing how many banks of error reportingMSRs are supported.15CMOVConditional Move Instructions. The conditional move instruction CMOV issupported. In addition, if x87 FPU is present as indicated by the CPUID.FPUfeature bit, then the FCOMI and FCMOV instructions are supported16PATPage Attribute Table. Page Attribute Table is supported. This featureaugments the Memory Type Range Registers (MTRRs), allowing anoperating system to specify attributes of memory accessed through a linearaddress on a 4KB granularity.17PSE-3636-Bit Page Size Extension.
4-MByte pages addressing physical memorybeyond 4 GBytes are supported with 32-bit paging. This feature indicatesthat upper bits of the physical address of a 4-MByte page are encoded inbits 20:13 of the page-directory entry. Such physical addresses are limitedby MAXPHYADDR and may be up to 40 bits in size.18PSNProcessor Serial Number.
The processor supports the 96-bit processoridentification number feature and the feature is enabled.19CLFSHCLFLUSH Instruction. CLFLUSH Instruction is supported.20ReservedReserved21DSDebug Store. The processor supports the ability to write debug informationinto a memory resident buffer. This feature is used by the branch tracestore (BTS) and precise event-based sampling (PEBS) facilities (see Chapter20, “Introduction to Virtual-Machine Extensions,” in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 3B).22ACPIThermal Monitor and Software Controlled Clock Facilities. The processorimplements internal MSRs that allow processor temperature to bemonitored and processor performance to be modulated in predefined dutycycles under software control.23MMXIntel MMX Technology. The processor supports the Intel MMX technology.24FXSRFXSAVE and FXRSTOR Instructions.
The FXSAVE and FXRSTOR instructionsare supported for fast save and restore of the floating point context.Presence of this bit also indicates that CR4.OSFXSR is available for anoperating system to indicate that it supports the FXSAVE and FXRSTORinstructions.3-216 Vol. 2ACPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MTable 3-16. More on Feature Information Returned in the EDX Register (Contd.)Bit #MnemonicDescription25SSESSE. The processor supports the SSE extensions.26SSE2SSE2. The processor supports the SSE2 extensions.27SSSelf Snoop. The processor supports the management of conflicting memorytypes by performing a snoop of its own cache structure for transactionsissued to the bus.28HTTMulti-Threading. The physical processor package is capable of supportingmore than one logical processor.29TMThermal Monitor.
The processor implements the thermal monitor automaticthermal control circuitry (TCC).30ReservedReserved31PBEPending Break Enable. The processor supports the use of the FERR#/PBE#pin when the processor is in the stop-clock state (STPCLK# is asserted) tosignal the processor that an interrupt is pending and that the processorshould return to normal operation to handle the interrupt. Bit 10 (PBEenable) in the IA32_MISC_ENABLE MSR enables this capability.INPUT EAX = 2: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDXWhen CPUID executes with EAX set to 2, the processor returns information about theprocessor’s internal TLBs, cache and prefetch hardware in the EAX, EBX, ECX, andEDX registers. The information is reported in encoded form and fall into the followingcategories:•The least-significant byte in register EAX (register AL) indicates the number oftimes the CPUID instruction must be executed with an input value of 2 to get acomplete description of the processor’s TLB/Cache/Prefetch hardware.
The IntelXeon processor 7400 series will return a 1.•The most significant bit (bit 31) of each register indicates whether the registercontains valid information (set to 0) or is reserved (set to 1).•If a register contains valid information, the information is contained in 1 bytedescriptors. There are four types of encoding values for the byte descriptor, theencoding type is noted in the second column of Table 3-17. Table 3-17 lists theencoding of these descriptors.
Note that the order of descriptors in the EAX, EBX,ECX, and EDX registers is not defined; that is, specific bytes are not designatedto contain descriptors for specific cache, prefetch, or TLB types. The descriptorsmay appear in any order. Note also a processor may report a general descriptortype (FFH) and not report any byte descriptor of “cache type“ via CPUID leaf 2.CPUID—CPU IdentificationVol. 2A 3-217INSTRUCTION SET REFERENCE, A-MTable 3-17. Encoding of CPUID Leaf 2 DescriptorsValueTypeDescription00HGeneral01HTLB02HTLBInstruction TLB: 4 MByte pages, fully associative, 2 entries03HTLBData TLB: 4 KByte pages, 4-way set associative, 64 entries04HTLBData TLB: 4 MByte pages, 4-way set associative, 8 entries05HTLBData TLB1: 4 MByte pages, 4-way set associative, 32 entries06HCache1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size08HCache1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte linesize09HCache1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size0AHCache1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line sizeNull descriptor, this byte contains no informationInstruction TLB: 4 KByte pages, 4-way set associative, 32 entries0BHTLB0CHCache1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size0DHCache1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size0EHCache1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size21HCache2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size22HCache3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 linesper sector23HCache3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines persector25HCache3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines persector29HCache3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines persector2CHCache1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size30HCache1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte linesize40HCacheNo 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rdlevel cache41HCache2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size42HCache2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size43HCache2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size44HCache2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size45HCache2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size3-218 Vol.
2AInstruction TLB: 4 MByte pages, 4-way set associative, 4 entriesCPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MTable 3-17. Encoding of CPUID Leaf 2 Descriptors (Contd.)ValueTypeDescription46HCache3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size47HCache3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size48HCache2nd-level cache: 3MByte, 12-way set associative, 64 byte line size49HCache3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeonprocessor MP, Family 0FH, Model 06H);2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size4AHCache3rd-level cache: 6MByte, 12-way set associative, 64 byte line size4BHCache3rd-level cache: 8MByte, 16-way set associative, 64 byte line size4CHCache3rd-level cache: 12MByte, 12-way set associative, 64 byte line size4DHCache3rd-level cache: 16MByte, 16-way set associative, 64 byte line size4EHCache2nd-level cache: 6MByte, 24-way set associative, 64 byte line size4FHTLB50HTLBInstruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries51HTLBInstruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries52HTLBInstruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries55HTLBInstruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries56HTLBData TLB0: 4 MByte pages, 4-way set associative, 16 entries57HTLBData TLB0: 4 KByte pages, 4-way associative, 16 entries59HTLBData TLB0: 4 KByte pages, fully associative, 16 entries5AHTLBData TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries5BHTLBData TLB: 4 KByte and 4 MByte pages, 64 entries5CHTLBData TLB: 4 KByte and 4 MByte pages,128 entries5DHTLBData TLB: 4 KByte and 4 MByte pages,256 entries60HCache1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size66HCache1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size67HCache1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size68HCache1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size70HCacheTrace cache: 12 K-μop, 8-way set associativeInstruction TLB: 4 KByte pages, 32 entries71HCacheTrace cache: 16 K-μop, 8-way set associative72HCacheTrace cache: 32 K-μop, 8-way set associative78HCache2nd-level cache: 1 MByte, 4-way set associative, 64byte line size79HCache2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 linesper sectorCPUID—CPU IdentificationVol.
2A 3-219INSTRUCTION SET REFERENCE, A-MTable 3-17. Encoding of CPUID Leaf 2 Descriptors (Contd.)ValueTypeDescription7AHCache2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 linesper sector7BHCache2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 linesper sector7CHCache2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines persector7DHCache2nd-level cache: 2 MByte, 8-way set associative, 64byte line size7FHCache2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size80HCache2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size82HCache2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size83HCache2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size84HCache2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size85HCache2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size86HCache2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size87HCache2nd-level cache: 1 MByte, 8-way set associative, 64 byte line sizeB0HTLBInstruction TLB: 4 KByte pages, 4-way set associative, 128 entriesB1HTLBInstruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entriesB2HTLBInstruction TLB: 4KByte pages, 4-way set associative, 64 entriesB3HTLBData TLB: 4 KByte pages, 4-way set associative, 128 entriesB4HTLBData TLB1: 4 KByte pages, 4-way associative, 256 entriesBAHTLBData TLB1: 4 KByte pages, 4-way associative, 64 entriesC0HTLBData TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entriesCAHSTLBShared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entriesE4HCache3rd-level cache: 8 MByte, 16-way set associative, 64 byte line sizeF0HPrefetchF1HPrefetch128-Byte prefetchingFFHGeneralCPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 toquery cache parameters64-Byte prefetchingExample 3-1.
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