Volume 2A Instruction Set Reference A-M (794101), страница 49
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Mapping of Brand Indices; andIntel 64 and IA-32 Processor Brand StringsBrand IndexBrand String00HThis processor does not support the brand identification feature01HIntel(R) Celeron(R) processor102HIntel(R) Pentium(R) III processor103HIntel(R) Pentium(R) III Xeon(R) processor; If processor signature =000006B1h, then Intel(R) Celeron(R) processor04HIntel(R) Pentium(R) III processor06HMobile Intel(R) Pentium(R) III processor-M07HMobile Intel(R) Celeron(R) processor108HIntel(R) Pentium(R) 4 processor09HIntel(R) Pentium(R) 4 processor0AHIntel(R) Celeron(R) processor10BHIntel(R) Xeon(R) processor; If processor signature = 00000F13h, then Intel(R)Xeon(R) processor MP0CHIntel(R) Xeon(R) processor MP0EHMobile Intel(R) Pentium(R) 4 processor-M; If processor signature =00000F13h, then Intel(R) Xeon(R) processor0FHMobile Intel(R) Celeron(R) processor111HMobile Genuine Intel(R) processor12HIntel(R) Celeron(R) M processor13HMobile Intel(R) Celeron(R) processor114HIntel(R) Celeron(R) processor15HMobile Genuine Intel(R) processor16HIntel(R) Pentium(R) M processor17HMobile Intel(R) Celeron(R) processor118H – 0FFHRESERVEDNOTES:1.
Indicates versions of these processors that were introduced after the Pentium IIICPUID—CPU IdentificationVol. 2A 3-227INSTRUCTION SET REFERENCE, A-MIA-32 Architecture CompatibilityCPUID is not supported in early models of the Intel486 processor or in any IA-32processor earlier than the Intel486 processor.OperationIA32_BIOS_SIGN_ID MSR ← Update with installed microcode revision number;CASE (EAX) OFEAX = 0:EAX ← Highest basic function input value understood by CPUID;EBX ← Vendor identification string;EDX ← Vendor identification string;ECX ← Vendor identification string;BREAK;EAX = 1H:EAX[3:0] ← Stepping ID;EAX[7:4] ← Model;EAX[11:8] ← Family;EAX[13:12] ← Processor type;EAX[15:14] ← Reserved;EAX[19:16] ← Extended Model;EAX[27:20] ← Extended Family;EAX[31:28] ← Reserved;EBX[7:0] ← Brand Index; (* Reserved if the value is zero. *)EBX[15:8] ← CLFLUSH Line Size;EBX[16:23] ← Reserved; (* Number of threads enabled = 2 if MT enable fuse set.
*)EBX[24:31] ← Initial APIC ID;ECX ← Feature flags; (* See Figure 3-6. *)EDX ← Feature flags; (* See Figure 3-7. *)BREAK;EAX = 2H:EAX ← Cache and TLB information;EBX ← Cache and TLB information;ECX ← Cache and TLB information;EDX ← Cache and TLB information;BREAK;EAX = 3H:EAX ← Reserved;EBX ← Reserved;ECX ← ProcessorSerialNumber[31:0];(* Pentium III processors only, otherwise reserved.
*)EDX ← ProcessorSerialNumber[63:32];(* Pentium III processors only, otherwise reserved. *3-228 Vol. 2ACPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-MBREAKEAX = 4H:EAX ← Deterministic Cache Parameters Leaf; (* See Table 3-12. *)EBX ← Deterministic Cache Parameters Leaf;ECX ← Deterministic Cache Parameters Leaf;EDX ← Deterministic Cache Parameters Leaf;BREAK;EAX = 5H:EAX ← MONITOR/MWAIT Leaf; (* See Table 3-12. *)EBX ← MONITOR/MWAIT Leaf;ECX ← MONITOR/MWAIT Leaf;EDX ← MONITOR/MWAIT Leaf;BREAK;EAX = 6H:EAX ← Thermal and Power Management Leaf; (* See Table 3-12.
*)EBX ← Thermal and Power Management Leaf;ECX ← Thermal and Power Management Leaf;EDX ← Thermal and Power Management Leaf;BREAK;EAX = 7H or 8H:EAX ← Reserved = 0;EBX ← Reserved = 0;ECX ← Reserved = 0;EDX ← Reserved = 0;BREAK;EAX = 9H:EAX ← Direct Cache Access Information Leaf; (* See Table 3-12. *)EBX ← Direct Cache Access Information Leaf;ECX ← Direct Cache Access Information Leaf;EDX ← Direct Cache Access Information Leaf;BREAK;EAX = AH:EAX ← Architectural Performance Monitoring Leaf; (* See Table 3-12.
*)EBX ← Architectural Performance Monitoring Leaf;ECX ← Architectural Performance Monitoring Leaf;EDX ← Architectural Performance Monitoring Leaf;BREAKEAX = BH:EAX ← Extended Topology Enumeration Leaf; (* See Table 3-12. *)EBX ← Extended Topology Enumeration Leaf;ECX ← Extended Topology Enumeration Leaf;EDX ← Extended Topology Enumeration Leaf;BREAK;CPUID—CPU IdentificationVol.
2A 3-229INSTRUCTION SET REFERENCE, A-MEAX = CH:EAX ← Reserved = 0;EBX ← Reserved = 0;ECX ← Reserved = 0;EDX ← Reserved = 0;BREAK;EAX = DH:EAX ← Processor Extended State Enumeration Leaf; (* See Table 3-12. *)EBX ← Processor Extended State Enumeration Leaf;ECX ← Processor Extended State Enumeration Leaf;EDX ← Processor Extended State Enumeration Leaf;BREAK;BREAK;EAX = 80000000H:EAX ← Highest extended function input value understood by CPUID;EBX ← Reserved;ECX ← Reserved;EDX ← Reserved;BREAK;EAX = 80000001H:EAX ← Reserved;EBX ← Reserved;ECX ← Extended Feature Bits (* See Table 3-12.*);EDX ← Extended Feature Bits (* See Table 3-12.
*);BREAK;EAX = 80000002H:EAX ← Processor Brand String;EBX ← Processor Brand String, continued;ECX ← Processor Brand String, continued;EDX ← Processor Brand String, continued;BREAK;EAX = 80000003H:EAX ← Processor Brand String, continued;EBX ← Processor Brand String, continued;ECX ← Processor Brand String, continued;EDX ← Processor Brand String, continued;BREAK;EAX = 80000004H:EAX ← Processor Brand String, continued;EBX ← Processor Brand String, continued;ECX ← Processor Brand String, continued;EDX ← Processor Brand String, continued;BREAK;3-230 Vol. 2ACPUID—CPU IdentificationINSTRUCTION SET REFERENCE, A-M= 80000005H:EAX ← Reserved = 0;EBX ← Reserved = 0;ECX ← Reserved = 0;EDX ← Reserved = 0;BREAK;EAX = 80000006H:EAX ← Reserved = 0;EBX ← Reserved = 0;ECX ← Cache information;EDX ← Reserved = 0;BREAK;EAX = 80000007H:EAX ← Reserved = 0;EBX ← Reserved = 0;ECX ← Reserved = 0;EDX ← Reserved = Misc Feature Flags;BREAK;EAX = 80000008H:EAX ← Reserved = Physical Address Size Information;EBX ← Reserved = Virtual Address Size Information;ECX ← Reserved = 0;EDX ← Reserved = 0;BREAK;EAX >= 40000000H and EAX <= 4FFFFFFFH:DEFAULT: (* EAX = Value outside of recognized range for CPUID.
*)(* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)EAX ← Reserved; (* Information returned for highest basic information leaf. *)EBX ← Reserved; (* Information returned for highest basic information leaf. *)ECX ← Reserved; (* Information returned for highest basic information leaf. *)EDX ← Reserved; (* Information returned for highest basic information leaf.
*)BREAK;ESAC;EAXFlags AffectedNone.Exceptions (All Operating Modes)#UDIf the LOCK prefix is used.In earlier IA-32 processors that do not support the CPUIDinstruction, execution of the instruction results in an invalidopcode (#UD) exception being generated.CPUID—CPU IdentificationVol. 2A 3-231INSTRUCTION SET REFERENCE, A-MCRC32 — Accumulate CRC32 ValueOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF2 0F 38 F0 /rCRC32 r32, r/m8AValidValidAccumulate CRC32 on r/m8.F2 REX 0F 38F0 /rCRC32 r32, r/m8*AValidN.E.Accumulate CRC32 on r/m8.F2 0F 38 F1 /rCRC32 r32, r/m16 AValidValidAccumulate CRC32 onr/m16.F2 0F 38 F1 /rCRC32 r32, r/m32 AValidValidAccumulate CRC32 onr/m32.AValidN.E.Accumulate CRC32 on r/m8.F2 REX.W 0F 38 CRC32 r64, r/m64 AF1 /rValidN.E.Accumulate CRC32 onr/m64.F2 REX.W 0F 38 CRC32 r64, r/m8F0 /rNOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionStarting with an initial value in the first operand (destination operand), accumulatesa CRC32 (polynomial 0x11EDC6F41) value for the second operand (source operand)and stores the result in the destination operand.
The source operand can be aregister or a memory location. The destination operand must be an r32 or r64register. If the destination is an r64 register, then the 32-bit result is stored in theleast significant double word and 00000000H is stored in the most significant doubleword of the r64 register.The initial value supplied in the destination operand is a double word integer storedin the r32 register or the least significant double word of the r64 register. To incrementally accumulate a CRC32 value, software retains the result of the previousCRC32 operation in the destination operand, then executes the CRC32 instructionagain with new input data in the source operand. Data contained in the sourceoperand is processed in reflected bit order. This means that the most significant bit ofthe source operand is treated as the least significant bit of the quotient, and so on,for all the bits of the source operand. Likewise, the result of the CRC operation isstored in the destination operand in reflected bit order.
This means that the mostsignificant bit of the resulting CRC (bit 31) is stored in the least significant bit of thedestination operand (bit 0), and so on, for all the bits of the CRC.3-232 Vol. 2ACRC32 — Accumulate CRC32 ValueINSTRUCTION SET REFERENCE, A-MOperationNotes:BIT_REFLECT64: DST[63-0] = SRC[0-63]BIT_REFLECT32: DST[31-0] = SRC[0-31]BIT_REFLECT16: DST[15-0] = SRC[0-15]BIT_REFLECT8: DST[7-0] = SRC[0-7]MOD2: Remainder from Polynomial division modulus 2CRC32 instruction for 64-bit source operand and 64-bit destination operand:TEMP1[63-0] Å BIT_REFLECT64 (SRC[63-0])TEMP2[31-0] Å BIT_REFLECT32 (DEST[31-0])TEMP3[95-0] Å TEMP1[63-0] << 32TEMP4[95-0] Å TEMP2[31-0] << 64TEMP5[95-0] Å TEMP3[95-0] XOR TEMP4[95-0]TEMP6[31-0] Å TEMP5[95-0] MOD2 11EDC6F41HDEST[31-0] Å BIT_REFLECT (TEMP6[31-0])DEST[63-32] Å 00000000HCRC32 instruction for 32-bit source operand and 32-bit destination operand:TEMP1[31-0] Å BIT_REFLECT32 (SRC[31-0])TEMP2[31-0] Å BIT_REFLECT32 (DEST[31-0])TEMP3[63-0] Å TEMP1[31-0] << 32TEMP4[63-0] Å TEMP2[31-0] << 32TEMP5[63-0] Å TEMP3[63-0] XOR TEMP4[63-0]TEMP6[31-0] Å TEMP5[63-0] MOD2 11EDC6F41HDEST[31-0] Å BIT_REFLECT (TEMP6[31-0])CRC32 instruction for 16-bit source operand and 32-bit destination operand:TEMP1[15-0] Å BIT_REFLECT16 (SRC[15-0])TEMP2[31-0] Å BIT_REFLECT32 (DEST[31-0])TEMP3[47-0] Å TEMP1[15-0] << 32TEMP4[47-0] Å TEMP2[31-0] << 16TEMP5[47-0] Å TEMP3[47-0] XOR TEMP4[47-0]TEMP6[31-0] Å TEMP5[47-0] MOD2 11EDC6F41HDEST[31-0] Å BIT_REFLECT (TEMP6[31-0])CRC32 instruction for 8-bit source operand and 64-bit destination operand:TEMP1[7-0] Å BIT_REFLECT8(SRC[7-0])TEMP2[31-0] Å BIT_REFLECT32 (DEST[31-0])TEMP3[39-0] Å TEMP1[7-0] << 32TEMP4[39-0] Å TEMP2[31-0] << 8TEMP5[39-0] Å TEMP3[39-0] XOR TEMP4[39-0]CRC32 — Accumulate CRC32 ValueVol.
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