Volume 2A Instruction Set Reference A-M (794101), страница 52
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In addition, depending on the operandconfiguration:•For operands xmm, mm: the instruction causes a transition from x87 FPU toMMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executedwhile an x87 FPU floating-point exception is pending, the exception is handledbefore the CVTPI2PD instruction is executed.•For operands xmm, m64: the instruction does not cause a transition to MMXtechnology and does not take x87 FPU exceptions.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);DEST[127:64] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);Intel C/C++ Compiler Intrinsic EquivalentCVTPI2PD __m128d _mm_cvtpi32_pd(__m64 a)3-250 Vol. 2ACVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP ValuesINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP ValuesVol.
2A 3-251INSTRUCTION SET REFERENCE, A-M#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)3-252 Vol. 2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP ValuesINSTRUCTION SET REFERENCE, A-MCVTPI2PS—Convert Packed Dword Integers to Packed Single-PrecisionFP ValuesOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 2A /rCVTPI2PS xmm,mm/m64AValidValidConvert two signeddoubleword integers frommm/m64 to two singleprecision floating-pointvalues in xmm.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed signed doubleword integers in the source operand (secondoperand) to two packed single-precision floating-point values in the destinationoperand (first operand).The source operand can be an MMX technology register or a 64-bit memory location.The destination operand is an XMM register.
The results are stored in the low quadword of the destination operand, and the high quadword remains unchanged. Whena conversion is inexact, the value returned is rounded according to the roundingcontrol bits in the MXCSR register.This instruction causes a transition from x87 FPU to MMX technology operation (thatis, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all0s [valid]). If this instruction is executed while an x87 FPU floating-point exception ispending, the exception is handled before the CVTPI2PS instruction is executed.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);DEST[63:32] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);(* High quadword of destination unchanged *)Intel C/C++ Compiler Intrinsic EquivalentCVTPI2PS__m128 _mm_cvtpi32_ps(__m128 a, __m64 b)CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP ValuesVol.
2A 3-253INSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsPrecision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)3-254 Vol.
2AFor a page fault.CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP ValuesINSTRUCTION SET REFERENCE, A-M#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP ValuesVol.
2A 3-255INSTRUCTION SET REFERENCE, A-MCVTPS2DQ—Convert Packed Single-Precision FP Values to PackedDword IntegersOpcodeInstructionOp/En66 0F 5B /rCVTPS2DQ xmm1, Axmm2/m12864-BitModeCompat/ DescriptionLeg ModeValidValidConvert four packed singleprecision floating-pointvalues from xmm2/m128 tofour packed signeddoubleword integers inxmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts four packed single-precision floating-point values in the source operand(second operand) to four packed signed doubleword integers in the destinationoperand (first operand).The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register.When a conversion is inexact, the value returned is rounded according to therounding control bits in the MXCSR register. If a converted result is larger than themaximum signed doubleword integer, the floating-point invalid exception is raised,and if this exception is masked, the indefinite integer value (80000000H) is returned.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);DEST[95:64] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64]);DEST[127:96] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96]);Intel C/C++ Compiler Intrinsic EquivalentCVTPS2DQ3-256 Vol.
2A__m128i _mm_cvtps_epi32(__m128 a)CVTPS2DQ—Convert Packed Single-Precision FP Values to Packed Dword IntegersINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsInvalid, Precision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.CVTPS2DQ—Convert Packed Single-Precision FP Values to Packed Dword IntegersVol.
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