Volume 2A Instruction Set Reference A-M (794101), страница 54
Текст из файла (страница 54)
See the summary chart at the beginning of thissection for encoding data and limits.OperationIF 64-Bit Mode and OperandSize = 64THENDEST[63:0] ← Convert_Double_Precision_Floating_Point_To_Integer64(SRC[63:0]);ELSEDEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);CVTSD2SI—Convert Scalar Double-Precision FP Value to IntegerVol. 2A 3-265INSTRUCTION SET REFERENCE, A-MFI;Intel C/C++ Compiler Intrinsic Equivalentint _mm_cvtsd_si32(__m128d a)SIMD Floating-Point ExceptionsInvalid, Precision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.3-266 Vol.
2ACVTSD2SI—Convert Scalar Double-Precision FP Value to IntegerINSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTSD2SI—Convert Scalar Double-Precision FP Value to IntegerVol.
2A 3-267INSTRUCTION SET REFERENCE, A-MCVTSD2SS—Convert Scalar Double-Precision FP Value to Scalar SinglePrecision FP ValueOpcodeInstructionOp/EnF2 0F 5A /rCVTSD2SS xmm1, Axmm2/m6464-BitModeCompat/ DescriptionLeg ModeValidValidConvert one doubleprecision floating-pointvalue in xmm2/m64 to onesingle-precision floatingpoint value in xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts a double-precision floating-point value in the source operand (secondoperand) to a single-precision floating-point value in the destination operand (firstoperand).The source operand can be an XMM register or a 64-bit memory location.
The destination operand is an XMM register. When the source operand is an XMM register, thedouble-precision floating-point value is contained in the low quadword of the register.The result is stored in the low doubleword of the destination operand, and the upper3 doublewords are left unchanged. When the conversion is inexact, the valuereturned is rounded according to the rounding control bits in the MXCSR register.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);(* DEST[127:32] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentCVTSD2SS__m128 _mm_cvtsd_ss(__m128 a, __m128d b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.3-268 Vol.
2ACVTSD2SS—Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP ValueINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.CVTSD2SS—Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP ValueVol.
2A 3-269INSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)3-270 Vol.
2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTSD2SS—Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP ValueINSTRUCTION SET REFERENCE, A-MCVTSI2SD—Convert Dword Integer to Scalar Double-Precision FP ValueOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF2 0F 2A /rCVTSI2SD xmm,r/m32AValidValidConvert one signeddoubleword integer fromr/m32 to one doubleprecision floating-pointvalue in xmm.F2 REX.W 0F 2A CVTSI2SD xmm,/rr/m64AValidN.E.Convert one signedquadword integer fromr/m64 to one doubleprecision floating-pointvalue in xmm.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts a signed doubleword integer (or signed quadword integer if operand size is64 bits) in the source operand (second operand) to a double-precision floating-pointvalue in the destination operand (first operand).
The source operand can be ageneral-purpose register or a memory location. The destination operand is an XMMregister. The result is stored in the low quadword of the destination operand, and thehigh quadword left unchanged.In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes theinstruction to 64-bit operands. See the summary chart at the beginning of thissection for encoding data and limits.OperationIF 64-Bit Mode And OperandSize = 64THENDEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:0]);(* DEST[127:64] unchanged *)ELSEDEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);(* DEST[127:64] unchanged *)FI;CVTSI2SD—Convert Dword Integer to Scalar Double-Precision FP ValueVol. 2A 3-271INSTRUCTION SET REFERENCE, A-MIntel C/C++ Compiler Intrinsic EquivalentCVTSI2SD__m128d _mm_cvtsi32_sd(__m128d a, int b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)3-272 Vol.
2AFor a page fault.CVTSI2SD—Convert Dword Integer to Scalar Double-Precision FP ValueINSTRUCTION SET REFERENCE, A-M#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTSI2SD—Convert Dword Integer to Scalar Double-Precision FP ValueVol.
2A 3-273INSTRUCTION SET REFERENCE, A-MCVTSI2SS—Convert Dword Integer to Scalar Single-Precision FP ValueOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF3 0F 2A /rCVTSI2SS xmm,r/m32AValidValidConvert one signeddoubleword integer fromr/m32 to one singleprecision floating-pointvalue in xmm.F3 REX.W 0F 2A CVTSI2SS xmm,/rr/m64AValidN.E.Convert one signedquadword integer fromr/m64 to one singleprecision floating-pointvalue in xmm.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts a signed doubleword integer (or signed quadword integer if operand size is64 bits) in the source operand (second operand) to a single-precision floating-pointvalue in the destination operand (first operand).
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
