Volume 2A Instruction Set Reference A-M (794101), страница 58
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2A 3-299INSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)3-300 Vol.
2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTTSS2SI—Convert with Truncation Scalar Single-Precision FP Value to Dword IntegerINSTRUCTION SET REFERENCE, A-MCWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword toQuadwordOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode99CWDAValidValidDX:AX ← sign-extend of AX.99CDQAValidValidEDX:EAX ← sign-extend ofEAX.REX.W + 99CQOAValidN.E.RDX:RAX← sign-extend ofRAX.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionDoubles the size of the operand in register AX, EAX, or RAX (depending on theoperand size) by means of sign extension and stores the result in registers DX:AX,EDX:EAX, or RDX:RAX, respectively.
The CWD instruction copies the sign (bit 15) ofthe value in the AX register into every bit position in the DX register. The CDQinstruction copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register. The CQO instruction (available in 64-bit mode only) copiesthe sign (bit 63) of the value in the RAX register into every bit position in the RDXregister.The CWD instruction can be used to produce a doubleword dividend from a wordbefore word division.
The CDQ instruction can be used to produce a quadword dividend from a doubleword before doubleword division. The CQO instruction can beused to produce a double quadword dividend from a quadword before a quadworddivision.The CWD and CDQ mnemonics reference the same opcode. The CWD instruction isintended for use when the operand-size attribute is 16 and the CDQ instruction forwhen the operand-size attribute is 32.
Some assemblers may force the operand sizeto 16 when CWD is used and to 32 when CDQ is used. Others may treat thesemnemonics as synonyms (CWD/CDQ) and use the current setting of the operandsize attribute to determine the size of values to be converted, regardless of themnemonic used.In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. The CQOmnemonics reference the same opcode as CWD/CDQ. See the summary chart at thebeginning of this section for encoding data and limits.CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to QuadwordVol. 2A 3-301INSTRUCTION SET REFERENCE, A-MOperationIF OperandSize = 16 (* CWD instruction *)THENDX ← SignExtend(AX);ELSE IF OperandSize = 32 (* CDQ instruction *)EDX ← SignExtend(EAX); FI;ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*)RDX ← SignExtend(RAX); FI;FI;Flags AffectedNone.Exceptions (All Operating Modes)#UD3-302 Vol.
2AIf the LOCK prefix is used.CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to QuadwordINSTRUCTION SET REFERENCE, A-MDAA—Decimal Adjust AL after AdditionOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode27DAAAInvalidValidDecimal adjust AL afteraddition.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionAdjusts the sum of two packed BCD values to create a packed BCD result. The ALregister is the implied source and destination operand. The DAA instruction is onlyuseful when it follows an ADD instruction that adds (binary addition) two 2-digit,packed BCD values and stores a byte result in the AL register.
The DAA instructionthen adjusts the contents of the AL register to contain the correct 2-digit, packedBCD result. If a decimal carry is detected, the CF and AF flags are set accordingly.This instruction executes as described above in compatibility mode and legacy mode.It is not valid in 64-bit mode.OperationIF 64-Bit ModeTHEN#UD;ELSEold_AL ← AL;old_CF ← CF;CF ← 0;IF (((AL AND 0FH) > 9) or AF = 1)THENAL ← AL + 6;CF ← old_CF or (Carry from AL ← AL + 6);AF ← 1;ELSEAF ← 0;FI;IF ((old_AL > 99H) or (old_CF = 1))THENAL ← AL + 60H;CF ← 1;DAA—Decimal Adjust AL after AdditionVol.
2A 3-303INSTRUCTION SET REFERENCE, A-MELSECF ← 0;FI;FI;ExampleADDAL, BLDAADAABefore: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXXAfter: AL=AEH BL=35H EFLAGS(0SZAPC)=110000Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101Flags AffectedThe CF and AF flags are set if the adjustment of the value results in a decimal carryin either digit of the result (see the “Operation” section above). The SF, ZF, and PFflags are set according to the result.
The OF flag is undefined.Protected Mode Exceptions#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#UDIf the LOCK prefix is used.Compatibility Mode Exceptions#UDIf the LOCK prefix is used.64-Bit Mode Exceptions#UD3-304 Vol. 2AIf in 64-bit mode.DAA—Decimal Adjust AL after AdditionINSTRUCTION SET REFERENCE, A-MDAS—Decimal Adjust AL after SubtractionOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode2FDASAInvalidValidDecimal adjust AL aftersubtraction.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionAdjusts the result of the subtraction of two packed BCD values to create a packedBCD result.
The AL register is the implied source and destination operand. The DASinstruction is only useful when it follows a SUB instruction that subtracts (binarysubtraction) one 2-digit, packed BCD value from another and stores a byte result inthe AL register. The DAS instruction then adjusts the contents of the AL register tocontain the correct 2-digit, packed BCD result. If a decimal borrow is detected, the CFand AF flags are set accordingly.This instruction executes as described above in compatibility mode and legacy mode.It is not valid in 64-bit mode.OperationIF 64-Bit ModeTHEN#UD;ELSEold_AL ← AL;old_CF ← CF;CF ← 0;IF (((AL AND 0FH) > 9) or AF = 1)THENAL ← AL - 6;CF ← old_CF or (Borrow from AL ← AL − 6);AF ← 1;ELSEAF ← 0;FI;IF ((old_AL > 99H) or (old_CF = 1))THENAL ← AL − 60H;DAS—Decimal Adjust AL after SubtractionVol.
2A 3-305INSTRUCTION SET REFERENCE, A-MCF ← 1;FI;FI;ExampleSUBAL, BLDAABefore: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXXAfter: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111Before: AL = EEH, BL = 47H, EFLAGS(OSZAPC) = 010111After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111Flags AffectedThe CF and AF flags are set if the adjustment of the value results in a decimal borrowin either digit of the result (see the “Operation” section above).
The SF, ZF, and PFflags are set according to the result. The OF flag is undefined.Protected Mode Exceptions#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#UDIf the LOCK prefix is used.Compatibility Mode Exceptions#UDIf the LOCK prefix is used.64-Bit Mode Exceptions#UD3-306 Vol. 2AIf in 64-bit mode.DAS—Decimal Adjust AL after SubtractionINSTRUCTION SET REFERENCE, A-MDEC—Decrement by 1OpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeFE /1DEC r/m8AValidValidDecrement r/m8 by 1.REX + FE /1*DEC r/m8AValidN.E.Decrement r/m8 by 1.FF /1DEC r/m16AValidValidDecrement r/m16 by 1.FF /1DEC r/m32AValidValidDecrement r/m32 by 1.REX.W + FF /1DEC r/m64AValidN.E.Decrement r/m64 by 1.48+rwDEC r16BN.E.ValidDecrement r16 by 1.48+rdDEC r32BN.E.ValidDecrement r32 by 1.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r, w)NANANABreg (r, w)NANANADescriptionSubtracts 1 from the destination operand, while preserving the state of the CF flag.The destination operand can be a register or a memory location.
This instructionallows a loop counter to be updated without disturbing the CF flag. (To perform adecrement operation that updates the CF flag, use a SUB instruction with an immediate operand of 1.)This instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48Hthrough 4FH are REX prefixes). Otherwise, the instruction’s 64-bit mode defaultoperation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.See the summary chart at the beginning of this section for encoding data and limits.OperationDEST ← DEST – 1;DEC—Decrement by 1Vol.
2A 3-307INSTRUCTION SET REFERENCE, A-MFlags AffectedThe CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to theresult.Protected Mode Exceptions#GP(0)If the destination operand is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.3-308 Vol.
2ADEC—Decrement by 1INSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.DEC—Decrement by 1Vol. 2A 3-309INSTRUCTION SET REFERENCE, A-MDIV—Unsigned DivideOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF6 /6DIV r/m8AValidValidUnsigned divide AX by r/m8,with result stored in AL ←Quotient, AH ← Remainder.REX + F6 /6DIV r/m8*AValidN.E.Unsigned divide AX by r/m8,with result stored in AL ←Quotient, AH ← Remainder.F7 /6DIV r/m16AValidValidUnsigned divide DX:AX byr/m16, with result stored inAX ← Quotient, DX ←Remainder.F7 /6DIV r/m32AValidValidUnsigned divide EDX:EAX byr/m32, with result stored inEAX ← Quotient, EDX ←Remainder.REX.W + F7 /6DIV r/m64AValidN.E.Unsigned divide RDX:RAXby r/m64, with result storedin RAX ← Quotient, RDX ←Remainder.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (w)NANANADescriptionDivides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL),DX:AX, EDX:EAX, or RDX:RAX registers.