Volume 2A Instruction Set Reference A-M (794101), страница 57
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2ACVTTPS2DQ—Convert with Truncation Packed Single-Precision FP Values to PackedDword IntegersINSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.CVTTPS2DQ—Convert with Truncation Packed Single-Precision FP Values to PackedDword IntegersVol. 2A 3-291INSTRUCTION SET REFERENCE, A-MCVTTPS2PI—Convert with Truncation Packed Single-Precision FPValues to Packed Dword IntegersOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F 2C /rCVTTPS2PI mm,xmm/m64AValidValidConvert two singleprecision floating-pointvalues from xmm/m64 totwo signed doublewordsigned integers in mm usingtruncation.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed single-precision floating-point values in the source operand(second operand) to two packed signed doubleword integers in the destinationoperand (first operand).
The source operand can be an XMM register or a 64-bitmemory location. The destination operand is an MMX technology register. When thesource operand is an XMM register, the two single-precision floating-point values arecontained in the low quadword of the register.When a conversion is inexact, a truncated (round toward zero) result is returned. If aconverted result is larger than the maximum signed doubleword integer, the floatingpoint invalid exception is raised, and if this exception is masked, the indefiniteinteger value (80000000H) is returned.This instruction causes a transition from x87 FPU to MMX technology operation (thatis, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all0s [valid]).
If this instruction is executed while an x87 FPU floating-point exception ispending, the exception is handled before the CVTTPS2PI instruction is executed.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);Intel C/C++ Compiler Intrinsic EquivalentCVTTPS2PI3-292 Vol. 2A__m64 _mm_cvttps_pi32(__m128 a)CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to PackedDword IntegersINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsInvalid, Precision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#MFIf there is a pending x87 FPU exception.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to PackedDword IntegersVol.
2A 3-293INSTRUCTION SET REFERENCE, A-M#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)3-294 Vol. 2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to PackedDword IntegersINSTRUCTION SET REFERENCE, A-MCVTTSD2SI—Convert with Truncation Scalar Double-Precision FP Valueto Signed IntegerOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF2 0F 2C /rCVTTSD2SI r32,xmm/m64AValidValidConvert one doubleprecision floating-pointvalue from xmm/m64 toone signed doublewordinteger in r32 usingtruncation.F2 REX.W 0F 2C CVTTSD2SI r64,/rxmm/m64AValidN.E.Convert one doubleprecision floating-pointvalue from xmm/m64 toone signedquadwordinteger in r64 usingtruncation.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts a double-precision floating-point value in the source operand (secondoperand) to a signed doubleword integer (or signed quadword integer if operand sizeis 64 bits) in the destination operand (first operand).
The source operand can be anXMM register or a 64-bit memory location. The destination operand is a generalpurpose register. When the source operand is an XMM register, the double-precisionfloating-point value is contained in the low quadword of the register.When a conversion is inexact, a truncated (round toward zero) result is returned. If aconverted result is larger than the maximum signed doubleword integer, the floatingpoint invalid exception is raised. If this exception is masked, the indefinite integervalue (80000000H) is returned.In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,R8-R15) when used with a REX.R prefix.
Use of the REX.W prefix promotes theinstruction to 64-bit operation. See the summary chart at the beginning of thissection for encoding data and limits.OperationIF 64-Bit Mode and OperandSize = 64THENDEST[63:0] ← Convert_Double_Precision_Floating_Point_To_CVTTSD2SI—Convert with Truncation Scalar Double-Precision FP Value to Signed IntegerVol. 2A 3-295INSTRUCTION SET REFERENCE, A-MInteger64_Truncate(SRC[63:0]);ELSEDEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);FI;Intel C/C++ Compiler Intrinsic Equivalentint _mm_cvttsd_si32(__m128d a)SIMD Floating-Point ExceptionsInvalid, Precision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.3-296 Vol.
2ACVTTSD2SI—Convert with Truncation Scalar Double-Precision FP Value to Signed IntegerINSTRUCTION SET REFERENCE, A-MIf the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.CVTTSD2SI—Convert with Truncation Scalar Double-Precision FP Value to Signed IntegerVol.
2A 3-297INSTRUCTION SET REFERENCE, A-MCVTTSS2SI—Convert with Truncation Scalar Single-Precision FP Valueto Dword IntegerOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF3 0F 2C /rCVTTSS2SI r32,xmm/m32AValidValidConvert one single-precisionfloating-point value fromxmm/m32 to one signeddoubleword integer in r32using truncation.F3 REX.W 0F 2C CVTTSS2SI r64,/rxmm/m32AValidN.E.Convert one single-precisionfloating-point value fromxmm/m32 to one signedquadword integer in r64using truncation.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts a single-precision floating-point value in the source operand (secondoperand) to a signed doubleword integer (or signed quadword integer if operand sizeis 64 bits) in the destination operand (first operand).
The source operand can be anXMM register or a 32-bit memory location. The destination operand is a generalpurpose register. When the source operand is an XMM register, the single-precisionfloating-point value is contained in the low doubleword of the register.When a conversion is inexact, a truncated (round toward zero) result is returned.
If aconverted result is larger than the maximum signed doubleword integer, the floatingpoint invalid exception is raised. If this exception is masked, the indefinite integervalue (80000000H) is returned.In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes theinstruction to 64-bit operation. See the summary chart at the beginning of thissection for encoding data and limits.OperationIF 64-Bit Mode and OperandSize = 64THENDEST[63:0] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);3-298 Vol.
2ACVTTSS2SI—Convert with Truncation Scalar Single-Precision FP Value to Dword IntegerINSTRUCTION SET REFERENCE, A-MELSEDEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);FI;Intel C/C++ Compiler Intrinsic Equivalentint _mm_cvttss_si32(__m128d a)SIMD Floating-Point ExceptionsInvalid, Precision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.CVTTSS2SI—Convert with Truncation Scalar Single-Precision FP Value to Dword IntegerVol.
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