Volume 2A Instruction Set Reference A-M (794101), страница 60
Текст из файла (страница 60)
2ADIVPS—Divide Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.DIVPS—Divide Packed Single-Precision Floating-Point ValuesVol. 2A 3-319INSTRUCTION SET REFERENCE, A-MDIVSD—Divide Scalar Double-Precision Floating-Point ValuesOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF2 0F 5E /rDIVSD xmm1,xmm2/m64AValidValidDivide low double-precisionfloating-point value n xmm1by low double-precisionfloating-point value inxmm2/mem64.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionDivides the low double-precision floating-point value in the destination operand (firstoperand) by the low double-precision floating-point value in the source operand(second operand), and stores the double-precision floating-point result in the destination operand.
The source operand can be an XMM register or a 64-bit memorylocation. The destination operand is an XMM register. The high quadword of the destination operand remains unchanged. See Chapter 11 in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 1, for an overview of a scalardouble-precision floating-point operation.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[63:0]← DEST[63:0] / SRC[63:0];(* DEST[127:64] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentDIVSD__m128d _mm_div_sd (m128d a, m128d b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.3-320 Vol.
2ADIVSD—Divide Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.DIVSD—Divide Scalar Double-Precision Floating-Point ValuesVol.
2A 3-321INSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)3-322 Vol. 2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.DIVSD—Divide Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MDIVSS—Divide Scalar Single-Precision Floating-Point ValuesOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF3 0F 5E /rDIVSS xmm1,xmm2/m32AValidValidDivide low single-precisionfloating-point value inxmm1 by low singleprecision floating-pointvalue in xmm2/m32.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionDivides the low single-precision floating-point value in the destination operand (firstoperand) by the low single-precision floating-point value in the source operand(second operand), and stores the single-precision floating-point result in the destination operand.
The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The three high-order doublewordsof the destination operand remain unchanged. See Chapter 10 in the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 1, for an overview of ascalar single-precision floating-point operation.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0]← DEST[31:0] / SRC[31:0];(* DEST[127:32] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentDIVSS__m128 _mm_div_ss(__m128 a, __m128 b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.DIVSS—Divide Scalar Single-Precision Floating-Point ValuesVol.
2A 3-323INSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.3-324 Vol.
2ADIVSS—Divide Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.DIVSS—Divide Scalar Single-Precision Floating-Point ValuesVol. 2A 3-325INSTRUCTION SET REFERENCE, A-MDPPD — Dot Product of Packed Double Precision Floating-Point ValuesOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F 3A 41 /ribDPPD xmm1,xmm2/m128,imm8AValidValidSelectively multiply packedDP floating-point valuesfrom xmm1 with packed DPfloating-point values fromxmm2, add and selectivelystore the packed DPfloating-point values toxmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)imm8NADescriptionConditionally multiplies the packed double-precision floating-point values in thedestination operand (first operand) with the packed double-precision floating-pointvalues in the source (second operand) depending on a mask extracted from bits[5:4] of the immediate operand (third operand).
If a condition mask bit is zero, thecorresponding multiplication is replaced by a value of 0.0.The two resulting double-precision values are summed into an intermediate result.The intermediate result is conditionally broadcasted to the destination using a broadcast mask specified by bits [1:0] of the immediate byte.If a broadcast mask bit is "1", the intermediate result is copied to the correspondingqword element in the destination operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.DPPS follows the NaN forwarding rules stated in the Software Developer’s Manual,vol. 1, table 4.7. These rules do not cover horizontal prioritization of NaNs. Horizontalpropagation of NaNs to the destination and the positioning of those NaNs in the destination is implementation dependent.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
