Volume 2A Instruction Set Reference A-M (794101), страница 56
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The source operand can be an XMM register or a 128-bitmemory location. The destination operand is an XMM register. The result is stored inthe low quadword of the destination operand and the high quadword is cleared to all0s.When a conversion is inexact, a truncated (round toward zero) result is returned.
If aconverted result is larger than the maximum signed doubleword integer, the floatingpoint invalid exception is raised, and if this exception is masked, the indefiniteinteger value (80000000H) is returned.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127-64]);DEST[127:64] ← 0000000000000000H;Intel C/C++ Compiler Intrinsic EquivalentCVTTPD2DQ__m128i _mm_cvttpd_epi32(__m128d a)CVTTPD2DQ—Convert with Truncation Packed Double-Precision FP Values to PackedDword IntegersVol.
2A 3-283INSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsInvalid, Precision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.3-284 Vol.
2ACVTTPD2DQ—Convert with Truncation Packed Double-Precision FP Values to PackedDword IntegersINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.CVTTPD2DQ—Convert with Truncation Packed Double-Precision FP Values to PackedDword IntegersVol. 2A 3-285INSTRUCTION SET REFERENCE, A-MCVTTPD2PI—Convert with Truncation Packed Double-Precision FPValues to Packed Dword IntegersOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode66 0F 2C /rCVTTPD2PI mm,xmm/m128AValidValidConvert two packer doubleprecision floating-pointvalues from xmm/m128 totwo packed signeddoubleword integers in mmusing truncation.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts two packed double-precision floating-point values in the source operand(second operand) to two packed signed doubleword integers in the destinationoperand (first operand).
The source operand can be an XMM register or a 128-bitmemory location. The destination operand is an MMX technology register.When a conversion is inexact, a truncated (round toward zero) result is returned. If aconverted result is larger than the maximum signed doubleword integer, the floatingpoint invalid exception is raised, and if this exception is masked, the indefiniteinteger value (80000000H) is returned.This instruction causes a transition from x87 FPU to MMX technology operation (thatis, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all0s [valid]). If this instruction is executed while an x87 FPU floating-point exception ispending, the exception is handled before the CVTTPD2PI instruction is executed.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[127:64]);Intel C/C++ Compiler Intrinsic EquivalentCVTTPD1PI__m64 _mm_cvttpd_pi32(__m128d a)3-286 Vol.
2ACVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to PackedDword IntegersINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsInvalid, Precision.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#MFIf there is a pending x87 FPU exception.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to PackedDword IntegersVol.
2A 3-287INSTRUCTION SET REFERENCE, A-M#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.3-288 Vol.
2ACVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to PackedDword IntegersINSTRUCTION SET REFERENCE, A-MCVTTPS2DQ—Convert with Truncation Packed Single-Precision FPValues to Packed Dword IntegersOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF3 0F 5B /rCVTTPS2DQxmm1,xmm2/m128AValidValidConvert four singleprecision floating-pointvalues from xmm2/m128 tofour signed doublewordintegers in xmm1 usingtruncation.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionConverts four packed single-precision floating-point values in the source operand(second operand) to four packed signed doubleword integers in the destinationoperand (first operand). The source operand can be an XMM register or a 128-bitmemory location.
The destination operand is an XMM register. When a conversion isinexact, a truncated (round toward zero) result is returned. If a converted result islarger than the maximum signed doubleword integer, the floating-point invalidexception is raised, and if this exception is masked, the indefinite integer value(80000000H) is returned.In 64-bit mode, use of the REX.R prefix permits this instruction to access additionalregisters (XMM8-XMM15).OperationDEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);DEST[95:64] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64]);DEST[127:96] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96]);Intel C/C++ Compiler Intrinsic EquivalentCVTTPS2DQ__m128i _mm_cvttps_epi32(__m128 a)SIMD Floating-Point ExceptionsInvalid, Precision.CVTTPS2DQ—Convert with Truncation Packed Single-Precision FP Values to PackedDword IntegersVol.
2A 3-289INSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.3-290 Vol.
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