Volume 2A Instruction Set Reference A-M (794101), страница 63
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Results Obtained from F2XM1ST(0) SRCST(0) DEST− 1.0 to −0− 0.5 to − 0−0−0+0+0+ 0 to +1.0+ 0 to 1.0Values other than 2 can be exponentiated using the following formula:xy ← 2(y ∗ log2x)This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationST(0) ← (2ST(0) − 1);FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IASource operand is an SNaN value or unsupported format.#DSource is a denormal value.F2XM1—Compute 2x–1Vol. 2A 3-343INSTRUCTION SET REFERENCE, A-M#UResult is too small for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-344 Vol.
2AF2XM1—Compute 2x–1INSTRUCTION SET REFERENCE, A-MFABS—Absolute ValueOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 E1FABSValidValidReplace ST with its absolute value.DescriptionClears the sign bit of ST(0) to create the absolute value of the operand. The followingtable shows the results obtained when creating the absolute value of various classesof numbers.Table 3-22. Results Obtained from FABSST(0) SRCST(0) DEST−•+•−F+F−0+0+0+0+F+F+•+•NaNNaNNOTES:F Means finite floating-point value.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationST(0) ← |ST(0)|;FPU Flags AffectedC1Set to 0 if stack underflow occurred; otherwise, set to 0.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.FABS—Absolute ValueVol.
2A 3-345INSTRUCTION SET REFERENCE, A-MReal-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-346 Vol. 2AFABS—Absolute ValueINSTRUCTION SET REFERENCE, A-MFADD/FADDP/FIADD—AddOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD8 /0FADD m32fpValidValidAdd m32fp to ST(0) and store resultin ST(0).DC /0FADD m64fpValidValidAdd m64fp to ST(0) and store resultin ST(0).D8 C0+iFADD ST(0), ST(i)ValidValidAdd ST(0) to ST(i) and store result inST(0).DC C0+iFADD ST(i), ST(0)ValidValidAdd ST(i) to ST(0) and store result inST(i).DE C0+iFADDP ST(i), ST(0)ValidValidAdd ST(0) to ST(i), store result inST(i), and pop the register stack.DE C1FADDPValidValidAdd ST(0) to ST(1), store result inST(1), and pop the register stack.DA /0FIADD m32intValidValidAdd m32int to ST(0) and storeresult in ST(0).DE /0FIADD m16intValidValidAdd m16int to ST(0) and storeresult in ST(0).DescriptionAdds the destination and source operands and stores the sum in the destination location.
The destination operand is always an FPU register; the source operand can be aregister or a memory location. Source operands in memory can be in single-precisionor double-precision floating-point format or in word or doubleword integer format.The no-operand version of the instruction adds the contents of the ST(0) register tothe ST(1) register. The one-operand version adds the contents of a memory location(either a floating-point or an integer value) to the contents of the ST(0) register. Thetwo-operand version, adds the contents of the ST(0) register to the ST(i) register orvice versa.
The value in ST(0) can be doubled by coding:FADD ST(0), ST(0);The FADDP instructions perform the additional operation of popping the FPU registerstack after storing the result. To pop the register stack, the processor marks theST(0) register as empty and increments the stack pointer (TOP) by 1. (The nooperand version of the floating-point add instructions always results in the registerstack being popped. In some assemblers, the mnemonic for this instruction is FADDrather than FADDP.)The FIADD instructions convert an integer source operand to double extended-precision floating-point format before performing the addition.FADD/FADDP/FIADD—AddVol. 2A 3-347INSTRUCTION SET REFERENCE, A-MThe table on the following page shows the results obtained when adding variousclasses of numbers, assuming that neither overflow nor underflow occurs.When the sum of two operands with opposite signs is 0, the result is +0, except forthe round toward −∞ mode, in which case the result is −0.
When the source operandis an integer 0, it is treated as a +0.When both operand are infinities of the same sign, the result is ∞ of the expectedsign. If both operands are infinities of opposite signs, an invalid-operation exceptionis generated. See Table 3-23.Table 3-23. FADD/FADDP/FIADD ResultsDEST-∞−F−0+0+F+∞NaN-∞-∞-∞-∞-∞*NaN− F or − I - ∞−FSRCSRC± F or ± 0 + ∞NaN-∞SRC−0-∞DEST−0±0DEST+∞NaN+0-∞DEST±0+0DEST+∞NaN+ F or + I - ∞± F or ± 0 SRCSRC+F+∞NaN+∞*+∞+∞+∞+∞+∞NaNNaNNaNNaNNaNNaNNaNNaNNaNNOTES:F Means finite floating-point value.I Means integer.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF Instruction = FIADDTHENDEST ← DEST + ConvertToDoubleExtendedPrecisionFP(SRC);ELSE (* Source operand is floating-point value *)DEST ← DEST + SRC;FI;IF Instruction = FADDPTHENPopRegisterStack;FI;3-348 Vol.
2AFADD/FADDP/FIADD—AddINSTRUCTION SET REFERENCE, A-MFPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#IS#IAStack underflow occurred.Operand is an SNaN value or unsupported format.Operands are infinities of unlike sign.#DSource operand is a denormal value.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.FADD/FADDP/FIADD—AddVol.
2A 3-349INSTRUCTION SET REFERENCE, A-M#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-350 Vol. 2AFADD/FADDP/FIADD—AddINSTRUCTION SET REFERENCE, A-MFBLD—Load Binary Coded DecimalOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionDF /4FBLD m80 decValidValidConvert BCD value to floating-point andpush onto the FPU stack.DescriptionConverts the BCD source operand into double extended-precision floating-pointformat and pushes the value onto the FPU stack.
The source operand is loadedwithout rounding errors. The sign of the source operand is preserved, including thatof −0.The packed BCD digits are assumed to be in the range 0 through 9; the instructiondoes not check for invalid digits (AH through FH). Attempting to load an invalidencoding produces an undefined result.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationTOP ← TOP − 1;ST(0) ← ConvertToDoubleExtendedPrecisionFP(SRC);FPU Flags AffectedC1Set to 1 if stack overflow occurred; otherwise, set to 0.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack overflow occurred.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.FBLD—Load Binary Coded DecimalVol.
2A 3-351INSTRUCTION SET REFERENCE, A-MReal-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-352 Vol.
2AFBLD—Load Binary Coded DecimalINSTRUCTION SET REFERENCE, A-MFBSTP—Store BCD Integer and PopOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionDF /6FBSTP m80bcdValidValidStore ST(0) in m80bcd and pop ST(0).DescriptionConverts the value in the ST(0) register to an 18-digit packed BCD integer, stores theresult in the destination operand, and pops the register stack. If the source value is anon-integral value, it is rounded to an integer value, according to rounding modespecified by the RC field of the FPU control word. To pop the register stack, theprocessor marks the ST(0) register as empty and increments the stack pointer (TOP)by 1.The destination operand specifies the address where the first byte destination valueis to be stored. The BCD value (including its sign bit) requires 10 bytes of space inmemory.The following table shows the results obtained when storing various classes ofnumbers in packed BCD format.Table 3-24. FBSTP ResultsST(0)DEST− • or Value Too Large for DEST Format*F≤−1−D−1 < F < -0**−0−0+0+0+ 0 < F < +1**F ≥ +1+D+ • or Value Too Large for DEST Format*NaN*NOTES:F Means finite floating-point value.D Means packed-BCD number.* Indicates floating-point invalid-operation (#IA) exception.** ±0 or ±1, depending on the rounding mode.If the converted value is too large for the destination format, or if the source operandis an ∞, SNaN, QNAN, or is in an unsupported format, an invalid-arithmetic-operandcondition is signaled.
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