Volume 2A Instruction Set Reference A-M (794101), страница 67
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2A 3-379INSTRUCTION SET REFERENCE, A-M#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-380 Vol.
2AFDIVR/FDIVRP/FIDIVR—Reverse DivideINSTRUCTION SET REFERENCE, A-MFFREE—Free Floating-Point RegisterOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionDD C0+iFFREE ST(i)ValidValidSets tag for ST(i) to empty.DescriptionSets the tag in the FPU tag register associated with register ST(i) to empty (11B).The contents of ST(i) and the FPU stack-top pointer (TOP) are not affected.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationTAG(i) ← 11B;FPU Flags AffectedC0, C1, C2, C3 undefined.Floating-Point ExceptionsNone.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FFREE—Free Floating-Point RegisterVol.
2A 3-381INSTRUCTION SET REFERENCE, A-MFICOM/FICOMP—Compare IntegerOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionDE /2FICOM m16intValidValidCompare ST(0) with m16int.DA /2FICOM m32intValidValidCompare ST(0) with m32int.DE /3FICOMP m16intValidValidCompare ST(0) with m16int and popstack register.DA /3FICOMP m32intValidValidCompare ST(0) with m32int and popstack register.DescriptionCompares the value in ST(0) with an integer source operand and sets the conditioncode flags C0, C2, and C3 in the FPU status word according to the results (see tablebelow).
The integer value is converted to double extended-precision floating-pointformat before the comparison is made.Table 3-31. FICOM/FICOMP ResultsConditionC3C2C0ST(0) > SRC000ST(0) < SRC001ST(0) = SRC100Unordered111These instructions perform an “unordered comparison.” An unordered comparisonalso checks the class of the numbers being compared (see “FXAM—ExamineModR/M” in this chapter). If either operand is a NaN or is in an undefined format, thecondition flags are set to “unordered.”The sign of zero is ignored, so that –0.0 ← +0.0.The FICOMP instructions pop the register stack following the comparison.
To pop theregister stack, the processor marks the ST(0) register empty and increments thestack pointer (TOP) by 1.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationCASE (relation of operands) OFST(0) > SRC:C3, C2, C0 ← 000;ST(0) < SRC:C3, C2, C0 ← 001;ST(0) = SRC:C3, C2, C0 ← 100;Unordered:C3, C2, C0 ← 111;3-382 Vol. 2AFICOM/FICOMP—Compare IntegerINSTRUCTION SET REFERENCE, A-MESAC;IF Instruction = FICOMPTHENPopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred; otherwise, set to 0.C0, C2, C3See table on previous page.Floating-Point Exceptions#ISStack underflow occurred.#IAOne or both operands are NaN values or have unsupportedformats.#DOne or both operands are denormal values.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.FICOM/FICOMP—Compare IntegerVol.
2A 3-383INSTRUCTION SET REFERENCE, A-M#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-384 Vol.
2AFICOM/FICOMP—Compare IntegerINSTRUCTION SET REFERENCE, A-MFILD—Load IntegerOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionDF /0FILD m16intValidValidPush m16int onto the FPU registerstack.DB /0FILD m32intValidValidPush m32int onto the FPU registerstack.DF /5FILD m64intValidValidPush m64int onto the FPU registerstack.DescriptionConverts the signed-integer source operand into double extended-precision floatingpoint format and pushes the value onto the FPU register stack. The source operandcan be a word, doubleword, or quadword integer. It is loaded without roundingerrors. The sign of the source operand is preserved.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationTOP ← TOP − 1;ST(0) ← ConvertToDoubleExtendedPrecisionFP(SRC);FPU Flags AffectedC1Set to 1 if stack overflow occurred; set to 0 otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack overflow occurred.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.FILD—Load IntegerVol.
2A 3-385INSTRUCTION SET REFERENCE, A-M#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-386 Vol.
2AFILD—Load IntegerINSTRUCTION SET REFERENCE, A-MFINCSTP—Increment Stack-Top PointerOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 F7FINCSTPValidValidIncrement the TOP field in the FPUstatus register.DescriptionAdds one to the TOP field of the FPU status word (increments the top-of-stackpointer). If the TOP field contains a 7, it is set to 0. The effect of this instruction is torotate the stack by one position. The contents of the FPU data registers and tagregister are not affected.
This operation is not equivalent to popping the stack,because the tag for the previous top-of-stack register is not marked empty.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF TOP = 7THEN TOP ← 0;ELSE TOP ← TOP + 1;FI;FPU Flags AffectedThe C1 flag is set to 0. The C0, C2, and C3 flags are undefined.Floating-Point ExceptionsNone.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.FINCSTP—Increment Stack-Top PointerVol. 2A 3-387INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-388 Vol.
2AFINCSTP—Increment Stack-Top PointerINSTRUCTION SET REFERENCE, A-MFINIT/FNINIT—Initialize Floating-Point UnitOpcodeInstruction64-BitModeCompat/Leg ModeDescription9B DB E3FINITValidValidInitialize FPU after checking for pendingunmasked floating-point exceptions.DB E3FNINIT*ValidValidInitialize FPU without checking forpending unmasked floating-pointexceptions.NOTES:* See IA-32 Architecture Compatibility section below.DescriptionSets the FPU control, status, tag, instruction pointer, and data pointer registers totheir default states. The FPU control word is set to 037FH (round to nearest, allexceptions masked, 64-bit precision). The status word is cleared (no exception flagsset, TOP is set to 0).
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