Volume 2A Instruction Set Reference A-M (794101), страница 71
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The result in register ST(0) has the same sign as the source operandST(1) and a magnitude less than +π.The FPATAN instruction returns the angle between the X axis and the line from theorigin to the point (X,Y), where Y (the ordinate) is ST(1) and X (the abscissa) isST(0). The angle depends on the sign of X and Y independently, not just on the signof the ratio Y/X. This is because a point (−X,Y) is in the second quadrant, resulting inan angle between π/2 and π, while a point (X,−Y) is in the fourth quadrant, resultingin an angle between 0 and −π/2. A point (−X,−Y) is in the third quadrant, giving anangle between −π/2 and −π.The following table shows the results obtained when computing the arctangent ofvarious classes of numbers, assuming that underflow does not occur.FPATAN—Partial ArctangentVol. 2A 3-413INSTRUCTION SET REFERENCE, A-MTable 3-35.
FPATAN ResultsST(0)ST(1)-•−F−0+0+F-•− 3π/4*− π/2− π/2− π/2−F-p−π to −π/2−π/2−π/2−0-p-p-p*+0+p+p+F+p+•+3π/4*NaNNaN+•NaN− π/2− π/4*NaN−π/2 to −0-0NaN− 0*−0−0NaN+ π*+ 0*+0+0NaN+π to +π/2+ π/2+π/2+π/2 to+0+0NaN+π/2+π/2+π/2+ π/2+ π/4*NaNNaNNaNNaNNaNNaNNaNNOTES:F Means finite floating-point value.* Table 8-10 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,specifies that the ratios 0/0 and •/• generate the floating-point invalid arithmetic-operationexception and, if this exception is masked, the floating-point QNaN indefinite value is returned.With the FPATAN instruction, the 0/0 or •/• value is actually not calculated using division.Instead, the arctangent of the two variables is derived from a standard mathematical formulation that is generalized to allow complex numbers as arguments.
In this complex variable formulation, arctangent(0,0) etc. has well defined values. These values are needed to develop a libraryto compute transcendental functions with complex arguments, based on the FPU functions thatonly allow floating-point values as arguments.There is no restriction on the range of source operands that FPATAN can accept.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityThe source operands for this instruction are restricted for the 80287 math coprocessor to the following range:0 ≤ |ST(1)| < |ST(0)| < +∞OperationST(1) ← arctan(ST(1) / ST(0));PopRegisterStack;3-414 Vol.
2AFPATAN—Partial ArctangentINSTRUCTION SET REFERENCE, A-MFPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IASource operand is an SNaN value or unsupported format.#DSource operand is a denormal value.#UResult is too small for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FPATAN—Partial ArctangentVol.
2A 3-415INSTRUCTION SET REFERENCE, A-MFPREM—Partial RemainderOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 F8FPREMValidValidReplace ST(0) with the remainder obtainedfrom dividing ST(0) by ST(1).DescriptionComputes the remainder obtained from dividing the value in the ST(0) register (thedividend) by the value in the ST(1) register (the divisor or modulus), and stores theresult in ST(0). The remainder represents the following value:Remainder ← ST(0) − (Q ∗ ST(1))Here, Q is an integer value that is obtained by truncating the floating-point numberquotient of [ST(0) / ST(1)] toward zero.
The sign of the remainder is the same as thesign of the dividend. The magnitude of the remainder is less than that of themodulus, unless a partial remainder was computed (as described below).This instruction produces an exact result; the inexact-result exception does not occurand the rounding control has no effect. The following table shows the resultsobtained when computing the remainder of various classes of numbers, assumingthat underflow does not occur.Table 3-36. FPREM ResultsST(1)ST(0)-•-F-0+0+F+•NaN-•******NaN-FST(0)-F or -0****-F or -0ST(0)NaN-0-0-0**-0-0NaN+0+0+0**+0+0NaN+FST(0)+F or +0****+F or +0ST(0)NaN+•******NaNNaNNaNNaNNaNNaNNaNNaNNaNNOTES:F Means finite floating-point value.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.** Indicates floating-point zero-divide (#Z) exception.When the result is 0, its sign is the same as that of the dividend.
When the modulusis ∞, the result is equal to the value in ST(0).3-416 Vol. 2AFPREM—Partial RemainderINSTRUCTION SET REFERENCE, A-MThe FPREM instruction does not compute the remainder specified in IEEE Std 754.The IEEE specified remainder can be computed with the FPREM1 instruction. TheFPREM instruction is provided for compatibility with the Intel 8087 and Intel287 mathcoprocessors.The FPREM instruction gets its name “partial remainder” because of the way itcomputes the remainder. This instruction arrives at a remainder through iterativesubtraction. It can, however, reduce the exponent of ST(0) by no more than 63 in oneexecution of the instruction.
If the instruction succeeds in producing a remainder thatis less than the modulus, the operation is complete and the C2 flag in the FPU statusword is cleared. Otherwise, C2 is set, and the result in ST(0) is called the partialremainder. The exponent of the partial remainder will be less than the exponent ofthe original dividend by at least 32.
Software can re-execute the instruction (usingthe partial remainder in ST(0) as the dividend) until C2 is cleared. (Note that whileexecuting such a remainder-computation loop, a higher-priority interrupting routinethat needs the FPU can force a context switch in-between the instructions in theloop.)An important use of the FPREM instruction is to reduce the arguments of periodicfunctions.
When reduction is complete, the instruction stores the three least-significant bits of the quotient in the C3, C1, and C0 flags of the FPU status word. This information is important in argument reduction for the tangent function (using a modulusof π/4), because it locates the original angle in the correct one of eight sectors of theunit circle.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationD ← exponent(ST(0)) – exponent(ST(1));IF D < 64THENQ ← Integer(TruncateTowardZero(ST(0) / ST(1)));ST(0) ← ST(0) – (ST(1) ∗ Q);C2 ← 0;C0, C3, C1 ← LeastSignificantBits(Q); (* Q2, Q1, Q0 *)ELSEC2 ← 1;N ← An implementation-dependent number between 32 and 63;QQ ← Integer(TruncateTowardZero((ST(0) / ST(1)) / 2(D − N)));ST(0) ← ST(0) – (ST(1) ∗ QQ ∗ 2(D − N));FI;FPREM—Partial RemainderVol.
2A 3-417INSTRUCTION SET REFERENCE, A-MFPU Flags AffectedC0Set to bit 2 (Q2) of the quotient.C1Set to 0 if stack underflow occurred; otherwise, set to leastsignificant bit of quotient (Q0).C2Set to 0 if reduction complete; set to 1 if incomplete.C3Set to bit 1 (Q1) of the quotient.Floating-Point Exceptions#ISStack underflow occurred.#IASource operand is an SNaN value, modulus is 0, dividend is ∞, orunsupported format.#DSource operand is a denormal value.#UResult is too small for destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-418 Vol.
2AFPREM—Partial RemainderINSTRUCTION SET REFERENCE, A-MFPREM1—Partial RemainderOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 F5FPREM1ValidValidReplace ST(0) with the IEEE remainderobtained from dividing ST(0) by ST(1).DescriptionComputes the IEEE remainder obtained from dividing the value in the ST(0) register(the dividend) by the value in the ST(1) register (the divisor or modulus), and storesthe result in ST(0). The remainder represents the following value:Remainder ← ST(0) − (Q ∗ ST(1))Here, Q is an integer value that is obtained by rounding the floating-point numberquotient of [ST(0) / ST(1)] toward the nearest integer value.
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