Volume 2A Instruction Set Reference A-M (794101), страница 74
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2A 3-435INSTRUCTION SET REFERENCE, A-MFSIN—SineOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 FEFSINValidValidReplace ST(0) with its sine.DescriptionComputes the sine of the source operand in register ST(0) and stores the result inST(0). The source operand must be given in radians and must be within the range −263 to +263. The following table shows the results obtained when taking the sine ofvarious classes of numbers, assuming that underflow does not occur.Table 3-40.
FSIN ResultsSRC (ST(0))DEST (ST(0))-•*−F− 1 to + 1−0−0+0+0+F- 1 to +1+•*NaNNaNNOTES:F Means finite floating-point value.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.If the source operand is outside the acceptable range, the C2 flag in the FPU statusword is set, and the value in register ST(0) remains unchanged. The instruction doesnot raise an exception when the source operand is out of range. It is up to theprogram to check the C2 flag for out-of-range conditions. Source values outside therange −263 to +263 can be reduced to the range of the instruction by subtracting anappropriate integer multiple of 2π or by using the FPREM instruction with a divisor of2π. See the section titled “Pi” in Chapter 8 of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1, for a discussion of the proper value to usefor π in performing such reductions.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF ST(0) < 263THENC2 ← 0;3-436 Vol.
2AFSIN—SineINSTRUCTION SET REFERENCE, A-MST(0) ← sin(ST(0));ELSE (* Source operand out of range *)C2 ← 1;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C2Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0.C0, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IASource operand is an SNaN value, ∞, or unsupported format.#DSource operand is a denormal value.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FSIN—SineVol.
2A 3-437INSTRUCTION SET REFERENCE, A-MFSINCOS—Sine and CosineOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 FBFSINCOSValidValidCompute the sine and cosine of ST(0);replace ST(0) with the sine, and push thecosine onto the register stack.DescriptionComputes both the sine and the cosine of the source operand in register ST(0),stores the sine in ST(0), and pushes the cosine onto the top of the FPU register stack.(This instruction is faster than executing the FSIN and FCOS instructions in succession.)The source operand must be given in radians and must be within the range −263 to+263.
The following table shows the results obtained when taking the sine and cosineof various classes of numbers, assuming that underflow does not occur.Table 3-41. FSINCOS ResultsSRCDESTST(0)ST(1) CosineST(0) Sine-•**−F− 1 to + 1− 1 to + 1−0+1−0+0+1+0+F− 1 to + 1− 1 to + 1+•**NaNNaNNaNNOTES:F Means finite floating-point value.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.If the source operand is outside the acceptable range, the C2 flag in the FPU statusword is set, and the value in register ST(0) remains unchanged. The instruction doesnot raise an exception when the source operand is out of range. It is up to theprogram to check the C2 flag for out-of-range conditions. Source values outside therange −263 to +263 can be reduced to the range of the instruction by subtracting anappropriate integer multiple of 2π or by using the FPREM instruction with a divisor of2π.
See the section titled “Pi” in Chapter 8 of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1, for a discussion of the proper value to usefor π in performing such reductions.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.3-438 Vol. 2AFSINCOS—Sine and CosineINSTRUCTION SET REFERENCE, A-MOperationIF ST(0) < 263THENC2 ← 0;TEMP ← cosine(ST(0));ST(0) ← sine(ST(0));TOP ← TOP − 1;ST(0) ← TEMP;ELSE (* Source operand out of range *)C2 ← 1;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred; set to 1 of stack overflowoccurs.Set if result was rounded up; cleared otherwise.C2Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0.C0, C3Undefined.Floating-Point Exceptions#ISStack underflow or overflow occurred.#IASource operand is an SNaN value, ∞, or unsupported format.#DSource operand is a denormal value.#UResult is too small for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.FSINCOS—Sine and CosineVol.
2A 3-439INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-440 Vol. 2AFSINCOS—Sine and CosineINSTRUCTION SET REFERENCE, A-MFSQRT—Square RootOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 FAFSQRTValidValidComputes square root of ST(0) and storesthe result in ST(0).DescriptionComputes the square root of the source value in the ST(0) register and stores theresult in ST(0).The following table shows the results obtained when taking the square root of variousclasses of numbers, assuming that neither overflow nor underflow occurs.Table 3-42.
FSQRT ResultsSRC (ST(0))DEST (ST(0))-•*−F*−0−0+0+0+F+F+•+•NaNNaNNOTES:F Means finite floating-point value.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationST(0) ← SquareRoot(ST(0));FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IASource operand is an SNaN value or unsupported format.FSQRT—Square RootVol.
2A 3-441INSTRUCTION SET REFERENCE, A-MSource operand is a negative value (except for −0).#DSource operand is a denormal value.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-442 Vol. 2AFSQRT—Square RootINSTRUCTION SET REFERENCE, A-MFST/FSTP—Store Floating Point ValueOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 /2FST m32fpValidValidCopy ST(0) to m32fp.DD /2FST m64fpValidValidCopy ST(0) to m64fp.DD D0+iFST ST(i)ValidValidCopy ST(0) to ST(i).D9 /3FSTP m32fpValidValidCopy ST(0) to m32fp and pop registerstack.DD /3FSTP m64fpValidValidCopy ST(0) to m64fp and pop registerstack.DB /7FSTP m80fpValidValidCopy ST(0) to m80fp and pop registerstack.DD D8+iFSTP ST(i)ValidValidCopy ST(0) to ST(i) and pop registerstack.DescriptionThe FST instruction copies the value in the ST(0) register to the destination operand,which can be a memory location or another register in the FPU register stack.
Whenstoring the value in memory, the value is converted to single-precision or doubleprecision floating-point format.The FSTP instruction performs the same operation as the FST instruction and thenpops the register stack. To pop the register stack, the processor marks the ST(0)register as empty and increments the stack pointer (TOP) by 1. The FSTP instructioncan also store values in memory in double extended-precision floating-point format.If the destination operand is a memory location, the operand specifies the addresswhere the first byte of the destination value is to be stored.
If the destinationoperand is a register, the operand specifies a register in the register stack relative tothe top of the stack.If the destination size is single-precision or double-precision, the significand of thevalue being stored is rounded to the width of the destination (according to therounding mode specified by the RC field of the FPU control word), and the exponentis converted to the width and bias of the destination format.
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