Volume 2A Instruction Set Reference A-M (794101), страница 77
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2A 3-457INSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-458 Vol.
2AFSUB/FSUBP/FISUB—SubtractINSTRUCTION SET REFERENCE, A-MFSUBR/FSUBRP/FISUBR—Reverse SubtractOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD8 /5FSUBR m32fpValidValidSubtract ST(0) from m32fp andstore result in ST(0).DC /5FSUBR m64fpValidValidSubtract ST(0) from m64fp andstore result in ST(0).D8 E8+iFSUBR ST(0), ST(i)ValidValidSubtract ST(0) from ST(i) andstore result in ST(0).DC E0+iFSUBR ST(i), ST(0)ValidValidSubtract ST(i) from ST(0) andstore result in ST(i).DE E0+iFSUBRP ST(i), ST(0)ValidValidSubtract ST(i) from ST(0), storeresult in ST(i), and pop registerstack.DE E1FSUBRPValidValidSubtract ST(1) from ST(0),store result in ST(1), and popregister stack.DA /5FISUBR m32intValidValidSubtract ST(0) from m32int andstore result in ST(0).DE /5FISUBR m16intValidValidSubtract ST(0) from m16int andstore result in ST(0).DescriptionSubtracts the destination operand from the source operand and stores the differencein the destination location.
The destination operand is always an FPU register; thesource operand can be a register or a memory location. Source operands in memorycan be in single-precision or double-precision floating-point format or in word ordoubleword integer format.These instructions perform the reverse operations of the FSUB, FSUBP, and FISUBinstructions. They are provided to support more efficient coding.The no-operand version of the instruction subtracts the contents of the ST(1) registerfrom the ST(0) register and stores the result in ST(1).
The one-operand versionsubtracts the contents of the ST(0) register from the contents of a memory location(either a floating-point or an integer value) and stores the result in ST(0). The twooperand version, subtracts the contents of the ST(i) register from the ST(0) registeror vice versa.The FSUBRP instructions perform the additional operation of popping the FPU registerstack following the subtraction. To pop the register stack, the processor marks theST(0) register as empty and increments the stack pointer (TOP) by 1. The nooperand version of the floating-point reverse subtract instructions always results inFSUBR/FSUBRP/FISUBR—Reverse SubtractVol. 2A 3-459INSTRUCTION SET REFERENCE, A-Mthe register stack being popped.
In some assemblers, the mnemonic for this instruction is FSUBR rather than FSUBRP.The FISUBR instructions convert an integer source operand to double extendedprecision floating-point format before performing the subtraction.The following table shows the results obtained when subtracting various classes ofnumbers from one another, assuming that neither overflow nor underflow occurs.Here, the DEST value is subtracted from the SRC value (SRC − DEST = result).When the difference between two operands of like sign is 0, the result is +0, exceptfor the round toward −∞ mode, in which case the result is −0. This instruction alsoguarantees that +0 − (−0) = +0, and that −0 − (+0) = −0.
When the source operand isan integer 0, it is treated as a +0.When one operand is ∞, the result is ∞ of the expected sign. If both operands are ∞ ofthe same sign, an invalid-operation exception is generated.Table 3-44. FSUBR/FSUBRP/FISUBR ResultsSRC-•−F or −I−0+0+F or +I+•NaN-•*+•+•+•+•+•NaN−F-•±F or ±0−DEST−DEST+F+•NaN−0-•SRC±0+0SRC+•NaN+0-•SRC−0±0SRC+•NaN+F-•−F−DEST−DEST±F or ±0+•NaN+•-•-•-•-•-•*NaNNaNNaNNaNNaNNaNNaNNaNNaNDESTNOTES:F Means finite floating-point value.I Means integer.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF Instruction = FISUBRTHENDEST ← ConvertToDoubleExtendedPrecisionFP(SRC) − DEST;ELSE (* Source operand is floating-point value *)DEST ← SRC − DEST; FI;3-460 Vol. 2AFSUBR/FSUBRP/FISUBR—Reverse SubtractINSTRUCTION SET REFERENCE, A-MIF Instruction = FSUBRPTHENPopRegisterStack; FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAOperand is an SNaN value or unsupported format.Operands are infinities of like sign.#DSource operand is a denormal value.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.FSUBR/FSUBRP/FISUBR—Reverse SubtractVol.
2A 3-461INSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-462 Vol.
2AFSUBR/FSUBRP/FISUBR—Reverse SubtractINSTRUCTION SET REFERENCE, A-MFTST—TESTOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 E4FTSTValidValidCompare ST(0) with 0.0.DescriptionCompares the value in the ST(0) register with 0.0 and sets the condition code flagsC0, C2, and C3 in the FPU status word according to the results (see table below).Table 3-45. FTST ResultsConditionC3C2C0ST(0) > 0.0000ST(0) < 0.0001ST(0) = 0.0100Unordered111This instruction performs an “unordered comparison.” An unordered comparison alsochecks the class of the numbers being compared (see “FXAM—Examine ModR/M” inthis chapter).
If the value in register ST(0) is a NaN or is in an undefined format, thecondition flags are set to “unordered” and the invalid operation exception is generated.The sign of zero is ignored, so that (– 0.0 ← +0.0).This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationCASE (relation of operands) OFNot comparable: C3, C2, C0 ← 111;ST(0) > 0.0:C3, C2, C0 ← 000;ST(0) < 0.0:C3, C2, C0 ← 001;ST(0) = 0.0:C3, C2, C0 ← 100;ESAC;FPU Flags AffectedC1Set to 0 if stack underflow occurred; otherwise, set to 0.C0, C2, C3See Table 3-45.Floating-Point Exceptions#ISFTST—TESTStack underflow occurred.Vol. 2A 3-463INSTRUCTION SET REFERENCE, A-M#IAThe source operand is a NaN value or is in an unsupportedformat.#DThe source operand is a denormal value.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-464 Vol.
2AFTST—TESTINSTRUCTION SET REFERENCE, A-MFUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point ValuesOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionDD E0+iFUCOM ST(i)ValidValidCompare ST(0) with ST(i).DD E1FUCOMValidValidCompare ST(0) with ST(1).DD E8+iFUCOMP ST(i)ValidValidCompare ST(0) with ST(i) and popregister stack.DD E9FUCOMPValidValidCompare ST(0) with ST(1) and popregister stack.DA E9FUCOMPPValidValidCompare ST(0) with ST(1) and popregister stack twice.DescriptionPerforms an unordered comparison of the contents of register ST(0) and ST(i) andsets condition code flags C0, C2, and C3 in the FPU status word according to theresults (see the table below). If no operand is specified, the contents of registersST(0) and ST(1) are compared.
The sign of zero is ignored, so that –0.0 is equal to+0.0.Table 3-46. FUCOM/FUCOMP/FUCOMPP ResultsComparison Results*C3C2C0ST0 > ST(i)000ST0 < ST(i)001ST0 = ST(i)100Unordered111NOTES:* Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.An unordered comparison checks the class of the numbers being compared (see“FXAM—Examine ModR/M” in this chapter). The FUCOM/FUCOMP/FUCOMPP instructions perform the same operations as the FCOM/FCOMP/FCOMPP instructions. Theonly difference is that the FUCOM/FUCOMP/FUCOMPP instructions raise the invalidarithmetic-operand exception (#IA) only when either or both operands are an SNaNor are in an unsupported format; QNaNs cause the condition code flags to be set tounordered, but do not cause an exception to be generated.
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