Volume 2A Instruction Set Reference A-M (794101), страница 78
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TheFCOM/FCOMP/FCOMPP instructions raise an invalid-operation exception when eitheror both of the operands are a NaN value of any kind or are in an unsupported format.As with the FCOM/FCOMP/FCOMPP instructions, if the operation results in an invalidarithmetic-operand exception being raised, the condition code flags are set only if theexception is masked.FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point ValuesVol. 2A 3-465INSTRUCTION SET REFERENCE, A-MThe FUCOMP instruction pops the register stack following the comparison operationand the FUCOMPP instruction pops the register stack twice following the comparisonoperation.
To pop the register stack, the processor marks the ST(0) register asempty and increments the stack pointer (TOP) by 1.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationCASE (relation of operands) OFST > SRC:C3, C2, C0 ← 000;ST < SRC:C3, C2, C0 ← 001;ST = SRC:C3, C2, C0 ← 100;ESAC;IF ST(0) or SRC = QNaN, but not SNaN or unsupported formatTHENC3, C2, C0 ← 111;ELSE (* ST(0) or SRC is SNaN or unsupported format *)#IA;IF FPUControlWord.IM = 1THENC3, C2, C0 ← 111;FI;FI;IF Instruction = FUCOMPTHENPopRegisterStack;FI;IF Instruction = FUCOMPPTHENPopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.C0, C2, C3See Table 3-46.Floating-Point Exceptions#IS3-466 Vol.
2AStack underflow occurred.FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point ValuesINSTRUCTION SET REFERENCE, A-M#IAOne or both operands are SNaN values or have unsupportedformats. Detection of a QNaN value in and of itself does not raisean invalid-operand exception.#DOne or both operands are denormal values.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point ValuesVol. 2A 3-467INSTRUCTION SET REFERENCE, A-MFXAM—Examine ModR/MOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 E5FXAMValidValidClassify value or number in ST(0).DescriptionExamines the contents of the ST(0) register and sets the condition code flags C0, C2,and C3 in the FPU status word to indicate the class of value or number in the register(see the table below).Table 3-47.
FXAM Results.ClassC3C2C0Unsupported000NaN001Normal finite number010Infinity011Zero100Empty101Denormal number110The C1 flag is set to the sign of the value in ST(0), regardless of whether the registeris empty or full.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationC1 ← sign bit of ST; (* 0 for positive, 1 for negative *)CASE (class of value or number in ST(0)) OFUnsupported:C3, C2, C0 ← 000;NaN:C3, C2, C0 ← 001;Normal:C3, C2, C0 ← 010;Infinity:C3, C2, C0 ← 011;Zero:C3, C2, C0 ← 100;Empty:C3, C2, C0 ← 101;Denormal:C3, C2, C0 ← 110;ESAC;3-468 Vol. 2AFXAM—Examine ModR/MINSTRUCTION SET REFERENCE, A-MFPU Flags AffectedC1Sign of value in ST(0).C0, C2, C3See Table 3-47.Floating-Point ExceptionsNone.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FXAM—Examine ModR/MVol.
2A 3-469INSTRUCTION SET REFERENCE, A-MFXCH—Exchange Register ContentsOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 C8+iFXCH ST(i)ValidValidExchange the contents of ST(0) andST(i).D9 C9FXCHValidValidExchange the contents of ST(0) andST(1).DescriptionExchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and ST(1) are exchanged.This instruction provides a simple means of moving values in the FPU register stackto the top of the stack [ST(0)], so that they can be operated on by those floatingpoint instructions that can only operate on values in ST(0).
For example, thefollowing instruction sequence takes the square root of the third register from the topof the register stack:FXCH ST(3);FSQRT;FXCH ST(3);This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF (Number-of-operands) is 1THENtemp ← ST(0);ST(0) ← SRC;SRC ← temp;ELSEtemp ← ST(0);ST(0) ← ST(1);ST(1) ← temp;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred; otherwise, set to 1.C0, C2, C3Undefined.Floating-Point Exceptions#IS3-470 Vol.
2AStack underflow occurred.FXCH—Exchange Register ContentsINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FXCH—Exchange Register ContentsVol.
2A 3-471INSTRUCTION SET REFERENCE, A-MFXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR StateOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg Mode0F AE /1FXRSTORm512byteAValidValidRestore the x87 FPU, MMX,XMM, and MXCSR registerstate from m512byte.REX.W+ 0F AE/1FXRSTOR64m512byteAValidN.E.Restore the x87 FPU, MMX,XMM, and MXCSR registerstate from m512byte.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r)NANANADescriptionReloads the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-bytememory image specified in the source operand.
This data should have been writtento memory previously using the FXSAVE instruction, and in the same format asrequired by the operating modes. The first byte of the data should be located on a16-byte boundary. There are three distinct layouts of the FXSAVE state map: one forlegacy and compatibility mode, a second format for 64-bit mode FXSAVE/FXRSTORwith REX.W=0, and the third format is for 64-bit mode with FXSAVE64/FXRSTOR64.Table 3-48 shows the layout of the legacy/compatibility mode state information inmemory and describes the fields in the memory image for the FXRSTOR and FXSAVEinstructions. Table 3-51 shows the layout of the 64-bit mode state information whenREX.W is set (FXSAVE64/FXRSTOR64).
Table 3-52 shows the layout of the 64-bitmode state information when REX.W is clear (FXSAVE/FXRSTOR).The state image referenced with an FXRSTOR instruction must have been savedusing an FXSAVE instruction or be in the same format as required by Table 3-48,Table 3-51, or Table 3-52. Referencing a state image saved with an FSAVE, FNSAVEinstruction or incompatible field layout will result in an incorrect state restoration.The FXRSTOR instruction does not flush pending x87 FPU exceptions. To check andraise exceptions when loading x87 FPU state information with the FXRSTOR instruction, use an FWAIT instruction after the FXRSTOR instruction.If the OSFXSR bit in control register CR4 is not set, the FXRSTOR instruction may notrestore the states of the XMM and MXCSR registers.
This behavior is implementationdependent.If the MXCSR state contains an unmasked exception with a corresponding status flagalso set, loading the register with the FXRSTOR instruction will not result in a SIMDfloating-point error condition being generated. Only the next occurrence of thisunmasked exception will result in the exception being generated.3-472 Vol. 2AFXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR StateINSTRUCTION SET REFERENCE, A-MBits 16 through 32 of the MXCSR register are defined as reserved and should be setto 0.
Attempting to write a 1 in any of these bits from the saved state image willresult in a general protection exception (#GP) being generated.Bytes 464:511 of an FXSAVE image are available for software use. FXRSTOR ignoresthe content of bytes 464:511 in an FXSAVE state image.Operation(x87 FPU, MMX, XMM7-XMM0, MXCSR) ← Load(SRC);x87 FPU and SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment. (See alignment check exception [#AC]below.)For an attempt to set reserved bits in MXCSR.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.If CR0.EM[bit 2] = 1.#UDIf CPUID.01H:EDX.FXSR[bit 24] = 0.If instruction is preceded by a LOCK prefix.#ACIf this exception is disabled a general protection exception(#GP) is signaled if the memory operand is not aligned on a 16byte boundary, as described above.
If the alignment checkexception (#AC) is enabled (and the CPL is 3), signaling of #ACis not guaranteed and may vary with implementation, asfollows. In all implementations where #AC is not signaled, ageneral protection exception is signaled in its place. In addition,the width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignmentcheck exception might be signaled for a 2-byte misalignment,whereas a general protection exception might be signaled for allother misalignments (4-, 8-, or 16-byte misalignments).#UDIf the LOCK prefix is used.FXRSTOR—Restore x87 FPU, MMX , XMM, and MXCSR StateVol. 2A 3-473INSTRUCTION SET REFERENCE, A-MReal-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.For an attempt to set reserved bits in MXCSR.#NMIf CR0.TS[bit 3] = 1.#UDIf CPUID.01H:EDX.FXSR[bit 24] = 0.If CR0.EM[bit 2] = 1.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#ACFor unaligned memory reference.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.For an attempt to set reserved bits in MXCSR.#MFIf there is a pending x87 FPU exception.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CPUID.01H:EDX.FXSR[bit 24] = 0.#ACIf this exception is disabled a general protection exception(#GP) is signaled if the memory operand is not aligned on a16-byte boundary, as described above.
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