Volume 2A Instruction Set Reference A-M (794101), страница 80
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2A 3-481INSTRUCTION SET REFERENCE, A-MTable 3-51. Layout of the 64-bit-mode FXSAVE64 Map(requires REX.W = 1) (Contd.)1514131211109876543210XMM2192XMM3208XMM4224XMM5240XMM6256XMM7272XMM8288XMM9304XMM10320XMM11336XMM12352XMM13368XMM14384XMM15400Reserved416Reserved432Reserved448Available464Available480Available496Table 3-52. Layout of the 64-bit-mode FXSAVE Map (REX.W = 0)151413Reserved12CSMXCSR_MASK11109876FPU IPFOPMXCSRReserved54ReservedFTW32FSW10FCWFPU DP016ReservedST0/MM032ReservedST1/MM148ReservedST2/MM264ReservedST3/MM3803-482 Vol. 2AFXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-MTable 3-52.
Layout of the 64-bit-mode FXSAVE Map (REX.W = 0) (Contd.) (Contd.)1514131211109876543210ReservedST4/MM496ReservedST5/MM5112ReservedST6/MM6128ReservedST7/MM7144XMM0160XMM1176XMM2192XMM3208XMM4224XMM5240XMM6256XMM7272XMM8288XMM9304XMM10320XMM11336XMM12352XMM13368XMM14384XMM15400Reserved416Reserved432Reserved448Available464Available480Available496OperationIF 64-Bit ModeTHENIF REX.W = 1THENFXSAVE—Save x87 FPU, MMX Technology, and SSE StateVol. 2A 3-483INSTRUCTION SET REFERENCE, A-MDEST ← Save64BitPromotedFxsave(x87 FPU, MMX, XMM7-XMM0,MXCSR);ELSEDEST ← Save64BitDefaultFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR);FI;ELSEDEST ← SaveLegacyFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR);FI;Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.
(See the description of the alignmentcheck exception [#AC] below.)#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.If CR0.EM[bit 2] = 1.#UDIf CPUID.01H:EDX.FXSR[bit 24] = 0.#UDIf the LOCK prefix is used.#ACIf this exception is disabled a general protection exception(#GP) is signaled if the memory operand is not aligned on a16-byte boundary, as described above. If the alignment checkexception (#AC) is enabled (and the CPL is 3), signaling of #ACis not guaranteed and may vary with implementation, asfollows. In all implementations where #AC is not signaled, ageneral protection exception is signaled in its place.
In addition,the width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignmentcheck exception might be signaled for a 2-byte misalignment,whereas a general protection exception might be signaled for allother misalignments (4-, 8-, or 16-byte misalignments).Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.If CR0.EM[bit 2] = 1.3-484 Vol.
2AFXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-M#UDIf CPUID.01H:EDX.FXSR[bit 24] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#ACFor unaligned memory reference.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#MFIf there is a pending x87 FPU exception.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.If CR0.EM[bit 2] = 1.#UDIf CPUID.01H:EDX.FXSR[bit 24] = 0.#ACIf this exception is disabled a general protection exception(#GP) is signaled if the memory operand is not aligned on a16-byte boundary, as described above.
If the alignment checkexception (#AC) is enabled (and the CPL is 3), signaling of #ACis not guaranteed and may vary with implementation, asfollows. In all implementations where #AC is not signaled, ageneral protection exception is signaled in its place. In addition,the width of the alignment check may also vary with implementation. For instance, for a given implementation, an alignmentcheck exception might be signaled for a 2-byte misalignment,whereas a general protection exception might be signaled for allother misalignments (4-, 8-, or 16-byte misalignments).If the LOCK prefix is used.FXSAVE—Save x87 FPU, MMX Technology, and SSE StateVol. 2A 3-485INSTRUCTION SET REFERENCE, A-MImplementation NoteThe order in which the processor signals general-protection (#GP) and page-fault(#PF) exceptions when they both occur on an instruction boundary is given in Table5-2 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume3B.
This order vary for FXSAVE for different processor implementations.3-486 Vol. 2AFXSAVE—Save x87 FPU, MMX Technology, and SSE StateINSTRUCTION SET REFERENCE, A-MFXTRACT—Extract Exponent and SignificandOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 F4FXTRACTValidValidSeparate value in ST(0) into exponent andsignificand, store exponent in ST(0), andpush the significand onto the registerstack.DescriptionSeparates the source value in the ST(0) register into its exponent and significand,stores the exponent in ST(0), and pushes the significand onto the register stack.Following this operation, the new top-of-stack register ST(0) contains the value ofthe original significand expressed as a floating-point value. The sign and significandof this value are the same as those found in the source operand, and the exponent is3FFFH (biased value for a true exponent of zero).
The ST(1) register contains thevalue of the original operand’s true (unbiased) exponent expressed as a floatingpoint value. (The operation performed by this instruction is a superset of the IEEErecommended logb(x) function.)This instruction and the F2XM1 instruction are useful for performing power and rangescaling operations. The FXTRACT instruction is also useful for converting numbers indouble extended-precision floating-point format to decimal representations (e.g., forprinting or displaying).If the floating-point zero-divide exception (#Z) is masked and the source operand iszero, an exponent value of –∞ is stored in register ST(1) and 0 with the sign of thesource operand is stored in register ST(0).This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationTEMP ← Significand(ST(0));ST(0) ← Exponent(ST(0));TOP← TOP − 1;ST(0) ← TEMP;FPU Flags AffectedC1Set to 0 if stack underflow occurred; set to 1 if stack overflowoccurred.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow or overflow occurred.FXTRACT—Extract Exponent and SignificandVol.
2A 3-487INSTRUCTION SET REFERENCE, A-M#IASource operand is an SNaN value or unsupported format.#ZST(0) operand is ±0.#DSource operand is a denormal value.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-488 Vol. 2AFXTRACT—Extract Exponent and SignificandINSTRUCTION SET REFERENCE, A-MFYL2X—Compute y ∗ log2xOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 F1FYL2XValidValidReplace ST(1) with (ST(1) ∗ log2ST(0))and pop the register stack.DescriptionComputes (ST(1) ∗ log2 (ST(0))), stores the result in resister ST(1), and pops theFPU register stack.
The source operand in ST(0) must be a non-zero positive number.The following table shows the results obtained when taking the log of various classesof numbers, assuming that neither overflow nor underflow occurs.Table 3-53. FYL2X ResultsST(0)ST(1)-•−F±0+0<+F<+1+1+F>+1+•NaN-•**+•+•*-•-•NaN−F****+F−0−F-•NaN−0***+0−0−0*NaN+0***−0+0+0*NaN+F****−F+0+F+•NaN+•**-•-•*+•+•NaNNaNNaNNaNNaNNaNNaNNaNNaNNaNNOTES:F Means finite floating-point value.* Indicates floating-point invalid-operation (#IA) exception.** Indicates floating-point zero-divide (#Z) exception.If the divide-by-zero exception is masked and register ST(0) contains ±0, the instruction returns ∞ with a sign that is the opposite of the sign of the source operand inregister ST(1).The FYL2X instruction is designed with a built-in multiplication to optimize the calculation of logarithms with an arbitrary positive base (b):logbx ← (log2b)–1 ∗ log2xThis instruction’s operation is the same in non-64-bit modes and 64-bit mode.FYL2X—Compute y * log2xVol.
2A 3-489INSTRUCTION SET REFERENCE, A-MOperationST(1) ← ST(1) ∗ log2ST(0);PopRegisterStack;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAEither operand is an SNaN or unsupported format.Source operand in register ST(0) is a negative finite value(not -0).#ZSource operand in register ST(0) is ±0.#DSource operand is a denormal value.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-490 Vol.
2AFYL2X—Compute y * log2xINSTRUCTION SET REFERENCE, A-MFYL2XP1—Compute y ∗ log2(x +1)OpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 F9FYL2XP1ValidValidReplace ST(1) with ST(1) ∗ log2(ST(0) +1.0) and pop the register stack.DescriptionComputes (ST(1) ∗ log2(ST(0) + 1.0)), stores the result in register ST(1), and popsthe FPU register stack. The source operand in ST(0) must be in the range:– ( 1 – 2 ⁄ 2 ) )to ( 1 – 2 ⁄ 2 )The source operand in ST(1) can range from −∞ to +∞.
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