Volume 2A Instruction Set Reference A-M (794101), страница 83
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The source operand can be a general-purpose register or a memory location.The action of this instruction depends on the operand size (dividend/divisor).Non-integral results are truncated (chopped) towards 0. The remainder is always lessthan the divisor in magnitude. Overflow is indicated with the #DE (divide error)exception rather than with the CF flag.In 64-bit mode, the instruction’s default operation size is 32 bits.
Use of the REX.Rprefix permits access to additional registers (R8-R15). Use of the REX.W prefixpromotes operation to 64 bits. In 64-bit mode when REX.W is applied, the instructionIDIV—Signed DivideVol. 2A 3-511INSTRUCTION SET REFERENCE, A-Mdivides the signed value in RDX:RAX by the source operand. RAX contains a 64-bitquotient; RDX contains a 64-bit remainder.See the summary chart at the beginning of this section for encoding data and limits.See Table 3-55.Table 3-55. IDIV ResultsOperand SizeDividendDivisorQuotientRemainderQuotient RangeWord/byteAXr/m8ALAH−128 to +127Doubleword/wordDX:AXr/m16AXDX−32,768 to+32,767Quadword/doublewordEDX:EAXr/m32EAXEDX−231 to 232 − 1Doublequadword/quadwordRDX:RAXr/m64RAXRDX−263 to 264 − 1OperationIF SRC = 0THEN #DE; (* Divide error *)FI;IF OperandSize = 8 (* Word/byte operation *)THENtemp ← AX / SRC; (* Signed division *)IF (temp > 7FH) or (temp < 80H)(* If a positive result is greater than 7FH or a negative result is less than 80H *)THEN #DE; (* Divide error *)ELSEAL ← temp;AH ← AX SignedModulus SRC;FI;ELSE IF OperandSize = 16 (* Doubleword/word operation *)THENtemp ← DX:AX / SRC; (* Signed division *)IF (temp > 7FFFH) or (temp < 8000H)(* If a positive result is greater than 7FFFHor a negative result is less than 8000H *)THEN#DE; (* Divide error *)ELSEAX ← temp;DX ← DX:AX SignedModulus SRC;FI;FI;3-512 Vol.
2AIDIV—Signed DivideINSTRUCTION SET REFERENCE, A-MELSE IF OperandSize = 32 (* Quadword/doubleword operation *)temp ← EDX:EAX / SRC; (* Signed division *)IF (temp > 7FFFFFFFH) or (temp < 80000000H)(* If a positive result is greater than 7FFFFFFFHor a negative result is less than 80000000H *)THEN#DE; (* Divide error *)ELSEEAX ← temp;EDX ← EDXE:AX SignedModulus SRC;FI;FI;ELSE IF OperandSize = 64 (* Doublequadword/quadword operation *)temp ← RDX:RAX / SRC; (* Signed division *)IF (temp > 7FFFFFFFFFFFH) or (temp < 8000000000000000H)(* If a positive result is greater than 7FFFFFFFFFFFHor a negative result is less than 8000000000000000H *)THEN#DE; (* Divide error *)ELSERAX ← temp;RDX ← RDE:RAX SignedModulus SRC;FI;FI;FI;Flags AffectedThe CF, OF, SF, ZF, AF, and PF flags are undefined.Protected Mode Exceptions#DEIf the source operand (divisor) is 0.The signed result (quotient) is too large for the destination.#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.IDIV—Signed DivideVol.
2A 3-513INSTRUCTION SET REFERENCE, A-MReal-Address Mode Exceptions#DEIf the source operand (divisor) is 0.The signed result (quotient) is too large for the destination.#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#DEIf the source operand (divisor) is 0.The signed result (quotient) is too large for the destination.#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#DEIf the source operand (divisor) is 0If the quotient is too large for the designated register.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-514 Vol.
2AIDIV—Signed DivideINSTRUCTION SET REFERENCE, A-MIMUL—Signed MultiplyOpcodeInstructionOp/En64-BitModeCompat/ DescriptionLeg ModeF6 /5IMUL r/m8*AValidValidAX← AL ∗ r/m byte.F7 /5IMUL r/m16AValidValidDX:AX ← AX ∗ r/m word.F7 /5IMUL r/m32AValidValidEDX:EAX ← EAX ∗ r/m32.REX.W + F7 /5IMUL r/m64AValidN.E.RDX:RAX ← RAX ∗ r/m64.0F AF /rIMUL r16, r/m16BValidValidword register ← wordregister ∗ r/m16.0F AF /rIMUL r32, r/m32BValidValiddoubleword register ←doubleword register ∗r/m32.REX.W + 0F AF/rIMUL r64, r/m64BValidN.E.Quadword register ←Quadword register ∗ r/m64.6B /r ibIMUL r16, r/m16,imm8CValidValidword register ← r/m16 ∗sign-extended immediatebyte.6B /r ibIMUL r32, r/m32,imm8CValidValiddoubleword register ←r/m32 ∗ sign-extendedimmediate byte.REX.W + 6B /r ib IMUL r64, r/m64,imm8CValidN.E.Quadword register ← r/m64∗ sign-extended immediatebyte.69 /r iwIMUL r16, r/m16,imm16CValidValidword register ← r/m16 ∗immediate word.69 /r idIMUL r32, r/m32,imm32CValidValiddoubleword register ←r/m32 ∗ immediatedoubleword.REX.W + 69 /r id IMUL r64, r/m64,imm32CValidN.E.Quadword register ← r/m64∗ immediate doubleword.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r, w)NANANABModRM:reg (r, w)ModRM:r/m (r)NANAIMUL—Signed MultiplyVol.
2A 3-515INSTRUCTION SET REFERENCE, A-MOp/EnOperand 1Operand 2Operand 3Operand 4CModRM:reg (r, w)ModRM:r/m (r)imm8/16/32NADescriptionPerforms a signed multiplication of two operands. This instruction has three forms,depending on the number of operands.•One-operand form — This form is identical to that used by the MUL instruction.Here, the source operand (in a general-purpose register or memory location) ismultiplied by the value in the AL, AX, EAX, or RAX register (depending on theoperand size) and the product is stored in the AX, DX:AX, EDX:EAX, or RDX:RAXregisters, respectively.•Two-operand form — With this form the destination operand (the firstoperand) is multiplied by the source operand (second operand).
The destinationoperand is a general-purpose register and the source operand is an immediatevalue, a general-purpose register, or a memory location. The product is thenstored in the destination operand location.•Three-operand form — This form requires a destination operand (the firstoperand) and two source operands (the second and the third operands). Here,the first source operand (which can be a general-purpose register or a memorylocation) is multiplied by the second source operand (an immediate value). Theproduct is then stored in the destination operand (a general-purpose register).When an immediate value is used as an operand, it is sign-extended to the length ofthe destination operand format.The CF and OF flags are set when significant bit (including the sign bit) are carriedinto the upper half of the result.
The CF and OF flags are cleared when the result(including the sign bit) fits exactly in the lower half of the result.The three forms of the IMUL instruction are similar in that the length of the productis calculated to twice the length of the operands. With the one-operand form, theproduct is stored exactly in the destination. With the two- and three- operand forms,however, the result is truncated to the length of the destination before it is stored inthe destination register. Because of this truncation, the CF or OF flag should be testedto ensure that no significant bits are lost.The two- and three-operand forms may also be used with unsigned operandsbecause the lower half of the product is the same regardless if the operands aresigned or unsigned.
The CF and OF flags, however, cannot be used to determine if theupper half of the result is non-zero.In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.Rprefix permits access to additional registers (R8-R15). Use of the REX.W prefixpromotes operation to 64 bits. Use of REX.W modifies the three forms of the instruction as follows.3-516 Vol. 2AIMUL—Signed MultiplyINSTRUCTION SET REFERENCE, A-M•One-operand form —The source operand (in a 64-bit general-purpose register ormemory location) is multiplied by the value in the RAX register and the product isstored in the RDX:RAX registers.•Two-operand form — The source operand is promoted to 64 bits if it is aregister or a memory location.
If the source operand is an immediate, it is signextended to 64 bits. The destination operand is promoted to 64 bits.•Three-operand form — The first source operand (either a register or a memorylocation) and destination operand are promoted to 64 bits.OperationIF (NumberOfOperands = 1)THEN IF (OperandSize = 8)THENAX ← AL ∗ SRC (* Signed multiplication *)IF AL = AXTHEN CF ← 0; OF ← 0;ELSE CF ← 1; OF ← 1; FI;ELSE IF OperandSize = 16THENDX:AX ← AX ∗ SRC (* Signed multiplication *)IF sign_extend_to_32 (AX) = DX:AXTHEN CF ← 0; OF ← 0;ELSE CF ← 1; OF ← 1; FI;ELSE IF OperandSize = 32THENEDX:EAX ← EAX ∗ SRC (* Signed multiplication *)IF EAX = EDX:EAXTHEN CF ← 0; OF ← 0;ELSE CF ← 1; OF ← 1; FI;ELSE (* OperandSize = 64 *)RDX:RAX ← RAX ∗ SRC (* Signed multiplication *)IF RAX = RDX:RAXTHEN CF ← 0; OF ← 0;ELSE CF ← 1; OF ← 1; FI;FI;FI;ELSE IF (NumberOfOperands = 2)THENtemp ← DEST ∗ SRC (* Signed multiplication; temp is double DEST size *)DEST ← DEST ∗ SRC (* Signed multiplication *)IF temp ≠ DESTTHEN CF ← 1; OF ← 1;ELSE CF ← 0; OF ← 0; FI;IMUL—Signed MultiplyVol.
2A 3-517INSTRUCTION SET REFERENCE, A-MELSE (* NumberOfOperands = 3 *)DEST ← SRC1 ∗ SRC2 (* Signed multiplication *)temp ← SRC1 ∗ SRC2 (* Signed multiplication; temp is double SRC1 size *)IF temp ≠ DESTTHEN CF ← 1; OF ← 1;ELSE CF ← 0; OF ← 0; FI;FI;FI;Flags AffectedFor the one operand form of the instruction, the CF and OF flags are set when significant bits are carried into the upper half of the result and cleared when the result fitsexactly in the lower half of the result. For the two- and three-operand forms of theinstruction, the CF and OF flags are set when the result must be truncated to fit in thedestination operand size and cleared when the result fits exactly in the destinationoperand size. The SF, ZF, AF, and PF flags are undefined.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.3-518 Vol.
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